Apparatus and methods for integrated power converter with high bandwidth

Patent metadata

Field	Value
Publication number	US-9847718-B2
Application number	US-201514814033-A
Country	US
Kind code	B2
Filing date	Jul 30, 2015
Priority date	Aug 4, 2014
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A DC-DC power converter includes a switched inductor power converter and a parallel linear voltage regulator. Two transistors are positioned in the switched inductor power converter to periodically set a bridge voltage thereby producing a square wave with a fixed frequency and variable duty cycle. An inductor and an output capacitor filter the bridge voltage so that only the average value of the bridge voltage is passed to the load. Parasitic impedance due to physical separation of the switched inductor power converter and the load is overcome by providing the parallel linear regulator with its own dedicated channel to the load.

First claim

What is claimed is:

1. An apparatus comprising:
a switched inductor power converter having a CMOS device and a low-pass filter, the low-pass filter having an input in electrical communication with an output of the CMOS device and an output in electrical communication with a power delivery channel, the power delivery channel for providing an output power to a load;
a voltage sense path in electrical communication with the power delivery channel and the power converter; and
a parallel linear voltage regulator in parallel electrically with the voltage sense path, wherein:
the parallel linear voltage regulator and the power converter are disposed on a common substrate, and
the parallel linear voltage regulator and the power converter have independent electrical interconnects that are electrically coupled at a connection proximal to the load at a location off of said common substrate.

2. The apparatus of claim 1 , wherein the linear voltage regulator is configured to provide a regulator current to the load in response to an output voltage error when an output voltage to the load is different than a target voltage for the load.

3. The apparatus of claim 2 , wherein the linear voltage regulator is configured to provide the regulator current only when the output voltage error is greater than a minimum value.

4. The apparatus of claim 1 , wherein the low-pass filter and the CMOS device are disposed on said common substrate.

5. The apparatus of claim 4 , wherein the low-pass filter comprises an inductor.

6. The apparatus of claim 4 , wherein the low-pass filter comprises a capacitor.

7. The apparatus of claim 1 , wherein the power converter further comprises a feedback controller, wherein an input of the feedback controller is in electrical communication with the voltage sense path and an output of the feedback controller is in electrical communication with the power converter.

8. The apparatus of claim 7 , wherein the feedback controller is configured so that the power converter responds to low frequency variations in the output voltage to the load, the low frequency variations lower than an LC resonance frequency of the low-pass filter.

9. The apparatus of claim 8 , wherein the linear voltage regulator is configured to respond to high frequency variations in the output voltage to the load, the high frequency variations greater than an LC resonance frequency of the low-pass filter.

10. The apparatus of claim 8 , wherein the power converter and the linear voltage regulator respond together to only a 10 MHz frequency band in variations in the output voltage to the load.

11. The apparatus of claim 1 , wherein the linear voltage regulator includes a CMOS amplifier.

12. The apparatus of claim 11 , wherein the CMOS amplifier includes a transistor having a source and a drain, wherein the source is electrically coupled to a DC power supply and the drain is electrically coupled to the power delivery channel.

13. The apparatus of claim 12 , wherein the linear voltage regulator further comprises a bias resistor electrically coupled to the transistor.

14. The apparatus of claim 13 , wherein the transistor is biased in a subthreshold region.

15. The apparatus of claim 12 , further comprising a capacitor in series with the transistor and an input of the linear voltage regulator, the input electrically coupled to the voltage sense path.

16. The apparatus of claim 11 , wherein the CMOS amplifier includes a NMOS transistor and a PMOS transistor in parallel electrically with one another.

17. The apparatus of claim 1 , wherein the load includes a current source.

18. The apparatus of claim 1 , wherein the CMOS device includes a PMOS transistor and a NMOS transistor, wherein the PMOS transistor has a PMOS source in electrical communication with a DC power supply and a PMOS drain in electrical communication with an input of the low-pass filter, and the NMOS transistor has a NMOS source in electrical communication with the input of the low-pass filter and the PMOS drain and a NMOS drain in electrical communication with a ground.

19. The apparatus of claim 1 , further comprising a parasitic inductor electrically coupled to said electrical interconnect for said parallel linear voltage regulator, said parasitic inductor disposed between said parallel linear voltage regulator and said connection.

20. The apparatus of claim 19 , wherein said parasitic inductor provides at least some electrical isolation between an output of said parallel linear voltage regulator and a capacitor in said low-pass filter.

21. A method of controlling power for a load, the method comprising:
in a switched inductor power converter, reducing a voltage of an input power supply to a reduced voltage suitable for the load;
delivering an output power to the load through a power delivery channel;
in a voltage sense path in electrical communication with the power delivery channel and the power converter, sensing an output voltage of the output power at a node proximal to the load;
in a parallel linear voltage regulator in parallel electrically with the voltage sense path, providing a regulator current to the load during an output voltage error when the output voltage to the load is different than a target voltage for the load, wherein
the parallel linear voltage regulator and the power converter are disposed on a common substrate, and
the parallel linear voltage regulator and the power converter have independent electrical interconnects that are electrically coupled at a connection proximal to the load at a location off of said common substrate.

22. The method of claim 21 , wherein reducing the voltage of the input power supply further comprises controlling a PMOS transistor gate and a NMOS transistor gate to provide a pulse-width modulated signal.

23. The method of claim 22 , further comprising filtering the pulse-width modulated signal in a low-pass filter.

24. The method of claim 23 , wherein the parallel linear voltage regulator is configured to provide the regulator current to the load only when a frequency of the output voltage error is less than a LC resonance frequency of the low-pass filter.

25. The method of claim 22 , further comprising adjusting the pulse-width modulated signal based on the sensed output voltage.

26. The method of claim 25 , wherein the pulse-width modulated signal is adjusted only when a frequency of the output voltage error is greater than a LC resonance frequency of a low-pass filter.

27. The method of claim 21 , further comprising biasing a transistor of the linear voltage regulator in a subthreshold region.

Assignees

• Ferric Inc
• Ferric Inc

Inventors

• Sturcken Noah
• Jew David
• Meyer Joe

Classifications

• H02M3/1584 Primary

  with a plurality of power processing stages connected in parallel · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M2001/0045

  Electricity · mapped topic

• H02M1/0045

  Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode · CPC title