Display substrate, display panel and display apparatus

Patent metadata

Field	Value
Publication number	US-11876102-B2
Application number	US-202318098773-A
Country	US
Kind code	B2
Filing date	Jan 19, 2023
Priority date	Feb 28, 2020
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

The present disclosure provides a display substrate, a display panel and a display apparatus, belonging to the field of display technology. The display substrate includes a base, a plurality of common electrodes and a plurality of common electrode lines, the common electrodes are distributed on the base in an array, the common electrode lines extend along a row direction, and each common electrode line is connected to a corresponding row of common electrodes. The common electrode line is connected to the common electrode through a conductive connection portion, and the conductive connection portion includes conductive structures stacked on top of one another in a plurality of layers. The display substrate can reduce the resistance between the common electrode and the common electrode line, thereby reducing the voltage difference between the common electrodes in the display substrate and improving the uniformity of the common voltage therein.

First claim

What is claimed is:

1. A display substrate, comprising:
a base;
a plurality of gate lines extending in a row direction;
a plurality of data lines extending in a column direction, wherein the plurality of data lines and the plurality of gate lines are on the base and cross over each other to define a plurality of sub-pixel units;
a plurality of common electrodes distributed on the base in an array; wherein each sub-pixel unit is provided with a common electrode therein;
a plurality of common electrode lines extending along the row direction, wherein the plurality of common electrode lines are connected to the plurality of common electrodes, respectively; and
a plurality of conductive connection portions, wherein one of the plurality of common electrode lines is correspondingly connected to at least one of the plurality of common electrodes through a corresponding conductive connection portion, and each conductive connection portion comprises a plurality of conductive structures stacked on top of one another in a plurality of layers; wherein
each conductive connection portion comprises a first end in direct contact with a corresponding common electrode and a second end in direct contact with a corresponding common electrode line, and a main body connected between the first end and the second end;
an orthographic projection of the main body on the base is parallel to an orthographic projection of the plurality of data lines on the base; and
a first distance between the main body and a data line connected to a sub-pixel unit corresponding to the main body is greater than a second distance between the data line and at least one of the first end or the second end.

2. The display substrate according to claim 1 , wherein
each of the plurality of sub-pixel units comprises: a thin film transistor; and
a third distance between the main body and a thin film transistor of a sub-pixel unit corresponding to the main body is greater than a fourth distance between the thin film transistor and at least one of the first end or the second end.

3. The display substrate according to claim 2 , wherein the first end is connected to the common electrode;
the conductive structures in the plurality of layers of the conductive connection portion comprise a first conductive structure and a second conductive structure; and
the first end comprises a pad in direct contact with the common electrode, a portion of the first conductive structure over the pad, and a portion of the second conductive structure over the portion of the first conductive structure.

4. The display substrate according to claim 3 , wherein the pad is a rectangular pad.

5. The display substrate according to claim 4 , wherein the sub-pixel unit comprises an opening area, and at least a portion of the rectangular pad close to the opening area is in direct contact with the second conductive structure.

6. The display substrate according to claim 5 , further comprising:
a first insulation layer on the rectangular pad wherein the portion of the first conductive structure is arranged on a portion of the first insulation layer corresponding to ¾ or ½ of an area of the rectangular pad at a side away from the opening area;
a second insulation layer on the first conductive structure, wherein the first insulation layer is in direct contact with the second insulation layer on ¼ or ½ of an area of the rectangular pad at a side close to the opening area, and the portion of the first conductive structure is in direct contact with the second insulation layer on ¾ or ½ of an area of the rectangular pad at a side away from the opening area; and
a via extending through the first insulation layer and the second insulation layer, wherein an orthographic projection of a center of the via on the base overlaps with an orthographic projection of a center of the rectangular pad on the base; and
wherein the portion of the second conductive structure is arranged on a portion of the second insulation layer corresponding to the rectangular pad, and the portion of the second conductive structure is in direct contact with the rectangular pad on ¼ or ½ of an area of the via at a side of the via close to the opening area.

7. The display substrate according to claim 5 , wherein
the sub-pixel unit further comprises a pixel electrode;
the pad and the gate line are arranged a the same layer, and are made of a same material; and
the portion of the first conductive structure is disposed in a same layer as a source electrode and a drain electrode of the thin film transistor, and is made of a same material as the drain electrode and/or the source electrode, and the portion of the second conductive structure is disposed in a same layer as the pixel electrode, and is made of a same material as the pixel electrode.

8. The display substrate according to claim 4 , wherein the portion of the first conductive structure is not arranged on approximately ¼ or ½ of an area of the pad.

9. The display substrate according to claim 8 , wherein
an orthographic projection of the portion of the second conductive structure on the base is within an orthographic projection of the pad on the base; and
an orthographic projection of the portion of the first conductive structure on the base overlaps with the orthographic projection of the pad on the base.

10. The display substrate according to claim 1 , wherein the gate line comprises a plurality of first gate line sub-portions and a plurality of second gate line sub-portions alternately arranged in an extending direction of the gate line;
in a direction perpendicular to the extending direction of the gate line, a width of each first gate line sub-portion is less than that of the second gate line sub-portion; and
an orthographic projection of each data line on the base partially overlaps with an orthographic projection of the first gate line sub-portion of the gate line, which crosses over the data line, on the base.

11. The display substrate according to claim 10 , wherein an orthographic projection of the conductive connection portion on the base partially overlaps with an orthographic projection of the first gate line sub-portion of a corresponding gate line on the base.

12. The display substrate according to claim 1 , wherein the common electrode line comprises a plurality of first common electrode line sub-portions and a plurality of second common electrode line sub-portions alternately arranged in an extending direction of the common electrode line;
in a direction perpendicular to the extending direction of the common electrode line, a width of the first common electrode line sub-portion is less than that of the second common electrode line sub-portion; and
an orthographic projection of each data line on the base partially overlaps with an orthographic projection of the first common electrode line sub-portion of a corresponding common electrode line on the base.

13. The display substrate according to claim 1 , wherein
each of the plurality of sub-pixel units comprises the conductive connection portion; and
the conductive connection portions in each column of sub-pixel units are all arranged on a same side of the column of sub-pixel units.

14. The display substrate according to claim 1 , wherein
each of the plurality of sub-pixel units comprises the conductive connection portion; and
the conductive connection portions in each column of sub-pixel units are alternately arranged on opposite sides of the column of sub-pixel units.

15. The display substrate according to claim 1 , wherein
the plurality of sub-pixel units comprise a plurality of columns of f

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Wang Xue
• Wang Xiao
• Yan Yan
• Wang Tingting
• Qi Yaya
• Li Xiaoying
• Ma Zhiqiang

Classifications

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H01L27/124 Primary

  Electricity · mapped topic

• G02F1/13629

  Multilayer wirings · CPC title