Liquid crystal display substrate and preparation method thereof
US-9874783-B2 · Jan 23, 2018 · US
Array substrate and method for manufacturing the same, and display apparatus
US10488710B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10488710-B2 |
| Application number | US-201715691203-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 30, 2017 |
| Priority date | Sep 28, 2016 |
| Publication date | Nov 26, 2019 |
| Grant date | Nov 26, 2019 |
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Abstract
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The present disclosure provides an array substrate and a method for manufacturing the same, and a display apparatus. The array substrate comprises a base, a layer structure provided on the base, and an alignment layer provided above the layer structure, wherein, the layer structure is provided with a recessed part, and distances from at least two positions of the alignment layer surrounding the recessed part to the base are different from each other.
First claim
Opening claim text (preview).
The invention claimed is: 1. An array substrate, comprising a base, a layer structure provided on the base, and an alignment layer provided above the layer structure, wherein, the layer structure is provided with a recessed part, and distances from at least two positions of a top surface of the alignment layer surrounding the recessed part to the base are different from each other, wherein the layer structure comprises a layer where a common electrode line is located, a gate insulating layer, a planarization layer and a layer where a common electrode is located, which are provided successively above the base, the recessed part is formed by a hole penetrating through the gate insulating layer and the planarization layer, a portion of the common electrode line and a portion of the base are exposed via the hole so that the common electrode is connected to the common electrode line through the hole. 2. The array substrate of claim 1 , wherein, distances from two positions of the alignment layer surrounding the recessed part to the base are different from each other, and the two positions are approximately symmetrical with respect to the recessed part. 3. The array substrate of claim 1 , wherein, the common electrode line is provided below a portion of the gate insulating layer surrounding the hole. 4. The array substrate of claim 1 , wherein, only the portion of the common electrode line is exposed via the hole. 5. A method for manufacturing an array substrate, the method comprises steps of: forming a layer structure on a base, and forming a recessed part in the layer structure; forming an alignment layer above the layer structure, wherein distances from at least two positions of a top surface of the alignment layer surrounding the recessed part to the base are different from each other, wherein the layer structure comprises a layer where a common electrode line is located, a gate insulating layer, a planarization layer and a layer where a common electrode is located, which are provided successively above the base, the recessed part is formed by a hole penetrating through the gate insulating layer and the planarization layer, a portion of the common electrode line and a portion of the base are exposed via the hole so that the common electrode is connected to the common electrode line through the hole. 6. The method of claim 5 , wherein, the common electrode line is provided below a portion of the gate insulating layer surrounding the hole. 7. The method of claim 5 , wherein, only the portion of the common electrode line is exposed via the hole. 8. A display apparatus, comprising an array substrate of claim 1 .
Assignees
Inventors
Classifications
common or background · CPC title
- G02F1/1337Primary
Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers · CPC title
in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title
characterised by their geometrical arrangement · CPC title
Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence) · CPC title
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Frequently asked questions
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- What does patent US10488710B2 cover?
- The present disclosure provides an array substrate and a method for manufacturing the same, and a display apparatus. The array substrate comprises a base, a layer structure provided on the base, and an alignment layer provided above the layer structure, wherein, the layer structure is provided with a recessed part, and distances from at least two positions of the alignment layer surrounding the…
- Who is the assignee on this patent?
- Boe Technology Group Co Ltd, Hefei Xinsheng Optoelectronics Technology Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification G02F1/1337. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Nov 26 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).