Optimization of soft bit windows based on signal and noise characteristics of memory cells

Patent metadata

Field	Value
Publication number	US-11875846-B2
Application number	US-202117534907-A
Country	US
Kind code	B2
Filing date	Nov 24, 2021
Priority date	Aug 7, 2020
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

A memory device to determine a voltage window to read soft bit data. For example, in response to a read command, the memory device can read a group of memory cells at a plurality of test voltages to determine signal and noise characteristics, which can be used to determine an optimized read voltage for reading hard bit data and a voltage window between a first voltage and a second voltage for reading soft bit data. The soft bit data identifies exclusive or (XOR) of results read from the group of memory cells at the first voltage and at the second voltage respective. The memory device can provide a response to the read command based on the hard bit data and the soft bit data.

First claim

What is claimed is:

1. A device, comprising:
memory cells; and
a logic circuit configured to:
receive data representative of signal and noise characteristics of the memory cells;
determine, based on the signal and noise characteristics, a first read voltage to read hard bit data from the memory cells; and
determine, based on the signal and noise characteristics, a voltage window between a second read voltage and a third read voltage to read soft bit data from the memory cells.

2. The device of claim 1 , comprising:
an integrated circuit package configured to enclose the memory cells and the logic circuit;
wherein the logic circuit is configured to determine the first read voltage, the second read voltage and the third read voltage in response to a read command received from outside of the integrated circuit package.

3. The device of claim 2 , comprising:
a read circuit configured to apply a respective read voltage on the memory cells and determine states of the memory cells when the memory cells are subjected to the respective read voltage;
wherein the logic circuit is configured to use the read circuit to determine the hard bit data by applying the first read voltage, and determine the soft bit data by applying the second read voltage and the third read voltage.

4. The device of claim 3 , wherein the soft bit data is based on an exclusive or (XOR) of first data read from the memory cells at the second read voltage and second data read from the memory cells at the third read voltage.

5. The device of claim 4 , wherein the signal and noise characteristics are based on a plurality of counts measured at a plurality of voltages respectively; and each respective count measured at a corresponding voltage is, among the memory cells, a number of first memory cells that has a predetermined state when the corresponding voltage is applied.

6. The device of claim 5 , wherein the voltage window is asymmetric with respect to the first read voltage calculated from the signal and noise characteristics.

7. The device of claim 1 , wherein at least a center of the voltage window relative to the first read voltage or a width of the voltage window is based on the signal and noise characteristics; and wherein the logic circuit is configured to determine the width of the voltage window based on the signal and noise characteristics.

8. The device of claim 1 , wherein at least a center of the voltage window relative to the first read voltage or a width of the voltage window is based on the signal and noise characteristics; and wherein the logic circuit is configured to determine the center of the voltage window based on the signal and noise characteristics.

9. The device of claim 1 , wherein at least a center of the voltage window relative to the first read voltage or a width of the voltage window is based on the signal and noise characteristics; and wherein the logic circuit is configured to identify the voltage window such that the second read voltage and the third read voltage are both within a range of the plurality of voltages.

10. The device of claim 5 , wherein the logic circuit is configured to determine the voltage window based on a predictive model trained using a machine learning technique.

11. The device of claim 5 , wherein the logic circuit is configured to determine the voltage window based on a set of predetermined rules and at least the signal and noise characteristics.

12. A method, comprising:
generating, in a device having memory cells, data representative of signal and noise characteristics of the memory cells;
determine, by a logic circuit of the device based on the signal and noise characteristics, a first read voltage to read hard bit data from the memory cells; and
determine, by the logic circuit based on the signal and noise characteristics, a voltage window between a second read voltage and a third read voltage to read soft bit data from the memory cells.

13. The method of claim 12 , wherein the device includes an integrated circuit package configured to enclose the memory cells and the logic circuit; the first read voltage, the second read voltage and the third read voltage are determined in response to a read command received from outside of the integrated circuit package; and the method further comprises:
applying, by a read circuit of the device, a respective read voltage on the memory cells to determine states of the memory cells when the memory cells are subjected to the respective read voltage;
wherein the hard bit data is determined via the read circuit applying the first read voltage;
wherein the soft bit data is determined via the read circuit applying the second read voltage to obtain first data and then the third read voltage to obtain second data; and
wherein the soft bit data is based on an exclusive or (XOR) of the first data and the second data.

14. The method of claim 13 , wherein the signal and noise characteristics are based on a plurality of counts measured at a plurality of voltages respectively; and each respective count measured at a corresponding voltage is, among the memory cells, a number of first memory cells that has a predetermined state when the corresponding voltage is applied.

15. The method of claim 14 , wherein the voltage window is asymmetric with respect to the first read voltage calculated from the signal and noise characteristics.

16. The method of claim 12 , wherein at least a center of the voltage window relative to the first read voltage or a width of the voltage window is based on the signal and noise characteristics; and wherein the voltage window is determined such that the second read voltage and the third read voltage are both within a range of the plurality of voltages.

17. The method of claim 12 , wherein at least a center of the voltage window relative to the first read voltage or a width of the voltage window is based on the signal and noise characteristics; and wherein the voltage window is determined based on a predictive model trained using a machine learning technique, or based on a set of predetermined rules.

18. An apparatus, comprising:
a processing device; and
a memory device enclosed within an integrated circuit package and connected to the processing device, the memory device having:
memory cells;
a read circuit configured to apply a respective read voltage on the memory cells and determine states of the memory cells when the memory cells are subjected to the respective read voltage;
a logic circuit configured to, in response to a read command from the processing device:
generate, using the read circuit, data representative of signal and noise characteristics of the memory cells;
determine, based on the signal and noise characteristics, a first read voltage;
generate, using the read circuit, first data of reading the memory cells using the first read voltage; and
determine, based on the signal and noise characteristics, a voltage window between a second read voltage and a third read voltage.

19. The apparatus of claim 18 , wherein the signal and noise characteristics are based on a plurality of counts measured at a plurality of voltages respectively; and each respective count measured at a corresponding voltage is, among the memory cells, a number of first memory cells that has a predetermined state when the corresponding voltage is applied.

20. The apparatus of claim 19 , wherein the logic circuit is configured to determine the voltage window such that the second read voltage and the third read voltage are both within a range

Assignees

• Micron Technology Inc

Inventors

• Fitzpatrick James
• Parthasarathy Sivagnanam
• Khayat Patrick Robert
• Alhussien Abdelhakim S

Classifications

• G11C11/5642 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G06F18/214

  Generating training patterns; Bootstrap methods, e.g. bagging or boosting · CPC title

• G06N20/00

  Machine learning · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G11C29/12005

  comprising voltage or current generators · CPC title