Packet processing system, method and device utilizing a port client chain

Patent metadata

Field	Value
Publication number	US-11874780-B2
Application number	US-202318105727-A
Country	US
Kind code	B2
Filing date	Feb 3, 2023
Priority date	Mar 30, 2015
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.

First claim

We claim:

1. A packet processing system comprising:
a non-transitory computer-readable packet memory organized into one or more memory banks;
a packet memory arbiter coupled with the one or more memory banks of the packet memory; and
a plurality of hierarchical clients of a client chain, wherein a first hierarchical client of the client chain is configured to forward the packet data to a second hierarchical client of the client chain based on an identifier of the packet data.

2. The system of claim 1 , wherein the plurality of hierarchical clients are each associated with a plurality of system ports and arbitrate between requests to access the packet memory from the plurality of system ports.

3. The system of claim 2 , wherein the client chain includes the packet memory arbiter and the client chain is only used to transmit the packet data to be read out from the packet memory and the packet memory arbiter is at the beginning of the client chain.

4. The system of claim 2 , wherein the client chain includes the packet memory arbiter and the client chain is used both to transmit the packet data to be read out from the packet memory and to transmit the packet data to be written into the packet memory, and further wherein the client chain forms a loop such that the packet memory arbiter is at the beginning and the end of the client chain.

5. The system of claim 2 , wherein the client chain includes the packet memory arbiter and the client chain is only used to transmit the packet data to be written into the packet memory and the packet memory arbiter is at the end of the client chain.

6. The system of claim 5 , wherein one or more of the plurality of hierarchical clients are directly coupled to the packet memory arbiter separately from the client chain via one or more secondary interfaces, and further wherein the secondary interfaces are only used to transmit the packet data to be read out from the packet memory.

7. The system of claim 6 , wherein the client chain further comprises one or more write clients that are configured to write the packet data into the packet memory.

8. The system of claim 7 , further comprising a plurality of additional system ports that are each associated with one of a plurality of additional hierarchical clients, wherein each of the plurality of additional hierarchical clients and the packet memory arbiter are serially communicatively coupled together via a plurality of additional interfaces thereby forming an additional client chain, and further wherein all of the plurality of additional hierarchical clients write the packet data to or read the packet data from the packet memory via the additional client chain.

9. The system of claim 8 , wherein, each cycle, the packet memory arbiter is configured to limit a sum of a number of the plurality of system ports and a number of the plurality of additional system ports that are granted access to write the packet data into the one or more memory banks of the packet memory such that the sum is equal to or less than a number of write ports of the one or more memory banks.

10. The system of claim 9 , wherein the additional client chain and the client chain have substantially the same latency.

11. The system of claim 10 , wherein the primary interfaces and the secondary interfaces are wide interfaces having a large bandwidth.

12. The system of claim 2 , wherein the plurality of hierarchical clients are configured to transmit the requests to access the packet memory to the packet memory arbiter, wherein each of the requests include a request tag that identifies one of the clients.

13. The system of claim 12 , wherein after granting one of the requests, the packet memory arbiter transmits a return tag to the one of the hierarchical clients, wherein the return tag identifies the one of the hierarchical clients, and further wherein the return tag indicates when to write packet data to or read packet data from the client chain.

14. A packet memory arbiter stored on a non-transitory computer-readable memory, wherein the packet memory arbiter is configured to:
arbitrate between a plurality of requests sent by a plurality of hierarchical clients of a client chain to access memory banks of a packet memory by granting one of the requests; and
after granting the one of the requests, transmitting a return tag to the hierarchical client that sent the request, wherein the return tag identifies the hierarchical client that sent the request, and further wherein the return tag indicates when to write packet data to or read packet data from the client chain.

15. The packet memory arbiter of claim 14 , wherein each of the plurality of hierarchical clients and the packet memory arbiter are serially communicatively coupled together via a plurality of primary interfaces thereby forming the client chain.

16. The packet memory arbiter of claim 15 , wherein the packet memory arbiter is further configured to at least one of: receive via the client chain packet data that is to be written into the packet memory from the plurality of hierarchical clients, and output, via the client chain, packet data that is to be read out from the packet memory to the plurality of hierarchical clients.

17. The packet memory arbiter of claim 16 , wherein the plurality of hierarchical clients arbitrate between requests to access the packet memory from a plurality of system ports.

18. The packet memory arbiter of claim 17 , wherein the client chain is only used to transmit the packet data to be read out from the packet memory and the packet memory arbiter is at the beginning of the client chain.

19. The packet memory arbiter of claim 17 , wherein the client chain is used both to transmit the packet data to be read out from the packet memory and to transmit the packet data to be written into the packet memory, and further wherein the client chain forms a loop such that the packet memory arbiter is at the beginning and the end of the client chain.

20. The packet memory arbiter of claim 17 , wherein the client chain is only used to transmit the packet data to be written into the packet memory and the packet memory arbiter is at the end of the client chain.

21. The packet memory arbiter of claim 20 , wherein one or more of the plurality of hierarchical clients are directly coupled to the packet memory arbiter separately from the client chain via one or more secondary interfaces, and further wherein the secondary interfaces are only used to transmit the packet data to be read out from the packet memory.

22. The packet memory arbiter of claim 21 , wherein the client chain further comprises one or more write clients that are configured to write the packet data into the packet memory.

23. The packet memory arbiter of claim 22 , wherein a plurality of additional system ports are each associated with one of a plurality of additional hierarchical clients, and further wherein each of the plurality of additional hierarchical clients and the packet memory arbiter are serially communicatively coupled together via a plurality of additional interfaces thereby forming an additional client chain, and further wherein all of the plurality of additional hierarchical clients write the packet data to or read the packet data from the packet memory via the additional client chain.

24. The packet memory arbiter of claim 23 , wherein, each cycle, the packet memory arbiter is configured to limit a sum of a number of the plurality of system ports and a number of t

Assignees

• Marvell Asia Pte Ltd
• Marvel Asia Pte Ltd

Inventors

• Musoll Enrique
• Daniel Tsahi

Classifications

• G06F13/1663 Primary

  Access to shared memory · CPC title

• G06F13/161

  with latency improvement · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• H04L45/126

  minimising geographical or physical path length · CPC title