Summing circuit and equalizer including the same

Patent metadata

Field	Value
Publication number	US-11870615-B2
Application number	US-202217835373-A
Country	US
Kind code	B2
Filing date	Jun 8, 2022
Priority date	Jun 11, 2021
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

Provided are a summing circuit and an equalizer including the summing circuit. The summing circuit includes: a reference signal generator generating a first reference signal and a second reference signal, based on a coefficient code; a first non-overlap clock buffer generating a first switching signal and a second switching signal by using the first reference signal; and a first current source receiving the first switching signal and the second switching signal generated by the first non-overlap clock buffer, generating a first output current by using a bias voltage, and outputting the first output current to an output line, wherein the first switching signal includes a switching signal and a complementary switching signal that is a complementary signal to the switching signal, and wherein a logic low period of the second switching signal is included in a logic high period of the complementary switching signal of the first switching signal.

First claim

What is claimed is:

1. An equalizer comprising a summing circuit,
wherein the summing circuit comprises:
a reference signal generator configured to generate a first reference signal and a second reference signal, based on a coefficient code;
a first non-overlap clock buffer configured to generate a first switching signal and a second switching signal by using the first reference signal; and
a first current source configured to receive the first switching signal and the second switching signal generated by the first non-overlap clock buffer, generate a first output current by using a bias voltage, and output the first output current to an output line,

wherein the first switching signal comprises a switching signal and a complementary switching signal that is a complementary signal to the switching signal, and
wherein a logic low period of the second switching signal is comprised in a logic high period of the complementary switching signal of the first switching signal.

2. The equalizer of claim 1 , wherein the equalizer is a decision feedback equalizer (DFE).

3. The equalizer of claim 1 , wherein the summing circuit further comprises:
a second non-overlap clock buffer configured to generate a first switching signal and a second switching signal by using the second reference signal; and
a second current source configured to receive the first switching signal and the second switching signal generated by the second non-overlap clock buffer, generate a second output current by using the bias voltage, and output the second output current to the output line.

4. The equalizer of claim 3 , wherein the first current source comprises:
a first switch configured to be switched according to the first switching signal;
a second switch configured to be switched according to the second switching signal; and
a current cell configured to generate the first output current according to the bias voltage.

5. The equalizer of claim 4 , wherein the first switch comprises a transmission gate,
the second switch comprises a P-type transistor connected between a power supply voltage terminal and a first node, and
the current cell comprises a P-type transistor configured to generate the output current according to a voltage of the first node.

6. The equalizer of claim 1 , wherein the first non-overlap clock buffer comprises a first circuit configured to generate the first switching signal and a second circuit configured to generate the second switching signal, and
each of the first circuit and the second circuit comprises a NAND gate and a plurality of inverters.

7. The equalizer of claim 6 , wherein the NAND gate of the first circuit receives the first reference signal and the second switching signal, and
the NAND gate of the second circuit receives a signal, into which the first reference signal is inverted, and the complementary switching signal.

8. The equalizer of claim 1 , further comprising:
a first latch circuit, wherein the first latch circuit and the summing circuit form an even data path configured to receive a reception data signal; and
a second latch circuit, wherein the second latch circuit and the summing circuit form an odd data path configured to receive the reception data signal,
wherein an even data signal output from the first latch circuit is input to the summing circuit comprised in the odd data path, and an odd data signal output from the second latch circuit is input to the summing circuit comprised in the even data path.

9. An equalizer comprising a summing circuit,
wherein the summing circuit comprises:
a reference signal generator configured to generate a reference signal, based on a coefficient code;
a non-overlap clock buffer configured to generate a first switching signal and a second switching signal by using the reference signal; and
a current source comprising a first switch configured to be switched by the first switching signal, a second switch configured to be switched by the second switching signal, and a current cell configured to generate an output current, and
wherein at least one of the first switch and the second switch is in an off-state.

10. The equalizer of claim 9 , wherein the first switch comprises a transmission gate,
the second switch comprises a P-type transistor connected between a power supply voltage terminal and a first node, and
the current cell comprises a P-type transistor configured to generate the output current according to a voltage of the first node.

11. The equalizer of claim 9 , wherein the first switching signal comprises a switching signal and a complementary switching signal that is a complementary signal to the switching signal.

12. The equalizer of claim 11 , wherein a logic low period of the second switching signal is comprised in a logic low period of the switching signal of the first switching signal.

13. The equalizer of claim 11 , wherein a logic high period of the switching signal of the first switching signal is comprised in a logic high period of the second switching signal.

14. The equalizer of claim 11 , wherein a logic low period of the second switching signal is comprised in a logic high period of the complementary switching signal of the first switching signal.

15. The equalizer of claim 11 , wherein a logic low period of the complementary switching signal of the first switching signal is comprised in a logic high period of the second switching signal.

16. The equalizer of claim 9 , wherein the non-overlap clock buffer comprises a first circuit configured to generate the first switching signal and a second circuit configured to generate the second switching signal, and
each of the first circuit and the second circuit comprises a NAND gate and a plurality of inverters.

17. A summing circuit comprising a current summing circuit,
wherein the current summing circuit comprises:
a reference signal generator configured to generate a plurality of reference signals, based on a coefficient code;
a plurality of non-overlap clock buffers configured to generate a plurality of first switching signals and a plurality of second switching signals by using the plurality of reference signals, respectively; and
a plurality of current sources, each comprising a first switch, a second switch, and a current cell, and
wherein at least one of the first switch and the second switch of each of the plurality of current sources is in an off-state.

18. The summing circuit of claim 17 , wherein the first switch comprises a transmission gate,
the second switch comprises a P-type transistor connected between a power supply voltage terminal and a first node, and
the current cell comprises a P-type transistor configured to generate an output current according to a voltage of the first node.

19. The summing circuit of claim 17 , wherein the first switching signal comprises a switching signal and a complementary switching signal that is a complementary signal to the switching signal, and
after a level of the switching signal of the first switching signal is changed from logic high to logic low, by changing a level of the second switching signal from logic high to logic low, the first switch is turned off, and then, the second switch is turned on.

20. The summing circuit of claim 17 , wherein the first switching signal comprises a switching signal and a complementary switching signal that is a complementary signal to the switching signal, and
after a level of the second switching signal is changed from logic low to logic high, by changing a level o

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ko Kyeongjoon
• Park Jaehyun
• Bae Junhan
• Song Gyeongseok
• Ryu Jongjae

Classifications

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K5/1515 Primary

  non-overlapping · CPC title

• H04L25/03146

  with a recursive structure (H04L25/03127 takes precedence) · CPC title