Circuits and methods for DFE with reduced area and power consumption

Patent metadata

Field	Value
Publication number	US-9806699-B2
Application number	US-201213590913-A
Country	US
Kind code	B2
Filing date	Aug 21, 2012
Priority date	Feb 6, 2009
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.

First claim

What is claimed is:

1. A combined slicer and summer circuit, comprising:
differential output lines connected to a plurality of differential currents to be summed, the differential currents forming continuous-time infinite impulse response (IIR) filter signals provided as feedback in a decision feedback equalizer (DFE);
a resettable current-comparator load directly coupled to the differential output lines, the current-comparator load configured to directly receive summed differential currents from the differential output lines; and
a passgate sample-and-hold that receives data input signals and produces a constant output during an evaluation phase, comprising a resistor to degenerate the input signals and a switch triggered by a clock signal to hold the data input signal during an evaluation phase and to reduce frequency-dependent loss,
wherein the resettable current-comparator load resets a differential voltage of the differential output lines to zero during a first phase of the clock signal and discharges parasitic capacitances of the output lines and further discharges the plurality of different currents onto the differential output lines during a second phase of the clock signal, such that depending on a sign of the summed differential currents, either a positive or negative differential voltage develops between the differential output lines, and
wherein a slicer turns on when an output common-mode falls below a threshold to latch a binary zero or one based on the positive or negative differential voltage.

2. The combined slicer and summer circuit as recited in claim 1 , wherein the differential currents include an input signal produced by a linear transconductor and at least one of a tap signal.

3. The combined slicer and summer circuit as recited in claim 2 , wherein the passgate sample-and-hold circuit is coupled to the linear transconductor to receive the input signal as switched by the clock signal to hold the input signal to the linear transconductor constant during the second phase of the clock signal.

4. A combined slicer and summer circuit, comprising:
differential output lines connected to a plurality of differential currents to be summed, the differential currents forming continuous-time infinite impulse response (IIR) filter signals provided as feedback in a decision feedback equalizer (DFE) and including an input signal produced by a linear transconductor and a tap signal;
a resettable current-comparator load directly coupled to the differential output lines, the current-comparator load configured to directly receive summed differential currents from the differential output lines; and
a passgate sample-and-hold that receives data input signals and produces a constant output during an evaluation phase, comprising a resistor to degenerate the input signals and a switch triggered by a clock signal to hold the data input signal during an evaluation phase and to reduce frequency-dependent loss,
wherein the resettable current-comparator load resets a differential voltage of the differential output lines to zero during a first phase of the clock signal and discharges parasitic capacitances of the output lines and further discharges the plurality of different currents onto the differential output lines during a second phase of the clock signal, such that depending on a sign of the summed differential currents, either a positive or negative differential voltage develops between the differential output lines,
wherein a slicer turns on when an output common-mode falls below a threshold to latch a binary zero or one based on the positive or negative differential voltage, and
wherein the passgate sample-and-hold is coupled to the linear transconductor to receive the input signal as switched by the clock signal to hold the input signal to the linear transconductor constant during the second phase of the clock signal.

Assignees

• Bulzacchelli John F
• Kim Byungsub
• IBM

Inventors

• Bulzacchelli John F
• Kim Byungsub

Classifications

• H03K3/35613 Primary

  the input circuit having a differential configuration · CPC title

• H03K3/356139

  with synchronous operation · CPC title

• H04L25/03146

  with a recursive structure (H04L25/03127 takes precedence) · CPC title

• H04L25/03267

  with decision feedback equalisers · CPC title

• H04L25/03006

  Arrangements for removing intersymbol interference · CPC title