Control circuit and method for controlling a data input/output

Patent metadata

Field	Value
Publication number	US-11870435-B2
Application number	US-202217979250-A
Country	US
Kind code	B2
Filing date	Nov 2, 2022
Priority date	Nov 3, 2021
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

A control circuit for controlling a data input/output is provided. The control circuit comprises a plurality of control level circuits that include a first control level circuit and a last control level circuit. Each control level circuit has a control element, with a number of control elements of the last control level circuit being greater than a number of control elements of the first control level circuit. Each control element is configured to receive a first control signal and a second control signal, and controls a current for the data input/output depending on the first and second control signals. The control circuit is configured to provide the first control signal to the control elements in a sequence starting at the first control level circuit and ending at the last control level circuit, and then to provide the second control signal to the last control level circuit in reverse order.

First claim

What is claimed is:

1. A control circuit for controlling data input/output, comprising:
a plurality of control level circuits that include a first control level circuit and a last control level circuit, each of the control level circuits having at least one control element;
wherein a first number of control elements of the first control level circuit is less than a second number of control elements of the last control level circuit;
wherein each of the control elements is configured to receive a first control signal and a second control signal and is further configured to control a current for the data input/output based on the first control signal and the second control signal;
wherein the control circuit is configured to provide the first control signal to the respective control elements in a sequence starting at the first control level circuit and ending at the last control level circuit, and then to provide the second control signal in a reverse order which starts at the last control level circuit and ends at the first control level circuit.

2. The control circuit as claimed in claim 1 ,
wherein each of the first number of control elements and the second number of control elements includes a transistor including a first gate terminal and a second gate terminal.

3. The control circuit as claimed in claim 2 ,
wherein the first control signal is provided at the first gate terminal of the transistor for each of the control elements.

4. The control circuit as claimed in claim 3 ,
wherein the second control signal is provided at the second gate terminal of the transistor for each of the control elements.

5. The control circuit as claimed in claim 2 ,
wherein the first gate terminal is arranged on a first side of a channel region of the transistor and the second gate terminal is arranged on a second side of the channel region located opposite the first side.

6. The control circuit as claimed in claim 2 ,
wherein the transistor is a metal oxide semiconductor field effect transistor (MOSFET).

7. The control circuit as claimed in claim 1 , wherein the control circuit is further configured to switch the second control signal to the control elements of the last control level circuit based on the first control signal and apply the second control signal concurrently with the first control signal, such that a current intensity for the data input/output is increased by provision of the second control signal compared to when only the first control signal is provided.

8. The control circuit as claimed in claim 7 , further comprising
at least one additional transistor which is configured to switch the second control signal.

9. The control circuit as claimed in claim 7 ,
wherein each of the control elements is configured, when providing only the first control signal, to supply only a portion of a maximum amount of current that the control element can supply for the data input/output.

10. The control circuit as claimed in claim 9 ,
wherein the portion is between 30% and 80%.

11. The control circuit as claimed in claim 9 ,
wherein the portion decreases in the sequence of the control level circuits.

12. The control circuit as claimed in claim 1 ,
wherein each of the control elements is configured to provide a maximum amount of current that the control element can provide for the data input/output when both the first control signal and the second control signal are provided to the control element.

13. The control circuit as claimed in claim 1 , further comprising:
an additional plurality of control level circuits corresponding to the plurality of control level circuits, except that the number of control elements in at least one control level circuit of the plurality of control level circuits differs from the number of control elements in the corresponding control level circuit of the additional plurality of control level circuits,
the additional plurality of control level circuits being connected in parallel to the plurality of control level circuits.

14. The control circuit as claimed in claim 13 , further comprising:
a pre-driver circuit configured to switch the plurality of control level circuits and/or the additional plurality of control level circuits into a switchable state.

15. The control circuit as claimed in claim 14 , further comprising:
a data input/output pad or a contactless data input/output element at which the current is supplied.

16. The control circuit as claimed in claim 15 ,
wherein the first control signal is provided via capacitive coupling.

17. A method for controlling a data input/output using a plurality of control level circuits including at least one first control level circuit and one last control level circuit, wherein each control level circuit has at least one control element, wherein a number of control elements of the last control level circuit is greater than a number of control elements of the first control level circuit, the method comprising:
providing a first control signal to each control element in a first sequence starting at the first control level circuit and ending at the last control level circuit, to provide current at a first current level for the data input/output; and
subsequently providing a second control signal in a second sequence to the control elements of at least the last control level circuit, to provide current at a second current level for the data input/output, the second current level being greater than the first current level.

18. The method as claimed in claim 17 ,
wherein each of the control elements includes a transistor including a first gate terminal and a second gate terminal.

19. The method as claimed in claim 18 ,
wherein the first gate terminals of the control elements are each arranged on a first side of a channel region and the second gate terminals are each arranged on a second side of the channel region located opposite the first side.

20. The method as claimed in claim 17 ,
wherein the second sequence has a reverse order relative to the first sequence;
wherein only the first control signal is provided to the control elements during the first sequence; and
wherein both the first control signal and the second control signal are provided concurrently to the control elements during the second sequence.

Assignees

• Infineon Technologies Ag

Inventors

• Unger Markus
• Pummerer Johannes

Classifications

• H03K17/6872 Primary

  using complementary field-effect transistors · CPC title

• H03K19/0175

  Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00) · CPC title

• H03K2217/9658

  Safety, e.g. fail-safe switching requiring a sequence of movements · CPC title

• H03K19/00361 Primary

  in field effect transistor circuits · CPC title

• H03K19/018507

  Interface arrangements · CPC title