Bus driver circuit with improved transition speed

Patent metadata

Field	Value
Publication number	US-9495317-B2
Application number	US-201314132831-A
Country	US
Kind code	B2
Filing date	Dec 18, 2013
Priority date	Dec 18, 2013
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A bus driver circuit may include a first and a second circuit node, wherein the first circuit node is operably coupled to a bus line, which causes a bus capacitance between the first and the second circuit node. A switching circuit is coupled to the first circuit node and configured to apply an output voltage between the first and the second circuit node. Thereby the bus capacitance is charged when a control signal indicates a dominant state. A discharge circuit comprises at least one resistor. The discharge circuit is coupled between the first and the second circuit node and configured to allow the bus capacitance to discharge via the resistor when the control signal indicates a recessive state. The switching circuit is further configured to provide a temporary current path for discharging the bus capacitance during a transition period from a dominant to a recessive state.

First claim

We claim:

1. A bus driver circuit comprising:
a first circuit node and a second circuit node, the first circuit node operably coupled to a bus line causing a bus capacitance between the first circuit node and the second circuit node;
a switching circuit coupled to the first circuit node and configured to apply an output voltage between the first circuit node and the second circuit node thus charging the bus capacitance, when a control signal indicates a dominant state;
a discharge circuit comprising at least one resistor, the discharge circuit being coupled between the first circuit node and the second circuit node and being configured to allow the bus capacitance to discharge via the resistor, when the control signal indicates a recessive state,
wherein the switching circuit is further being configured to provide, in addition to the discharge circuit, a temporary current path for discharging the bus capacitance during a transition period from a dominant to a recessive state.

2. The bus driver circuit of claim 1 , wherein the second circuit node is a supply node receiving a supply voltage; the first circuit node forming a driver output to allow single-ended signaling via the bus.

3. The bus driver circuit of claim 1 , wherein the first node is coupled to a first bus line and the second node is coupled to a second bus line; the first circuit node and the second node forming a driver output to allow differential signaling via the bus lines.

4. The bus driver circuit of claim 1 , wherein the switching circuit comprises at least one first transistor coupled to the first circuit node and configured to apply the output voltage at the first circuit node in accordance with the control signal.

5. The bus driver circuit of claim 1 , wherein the switching circuit comprises at least one first transistor coupled to the first circuit node and at least one second transistor coupled to the second circuit node; the first transistor and the second transistor being configured to apply the output voltage between the first and the second circuit node in accordance with the control signal.

6. The bus driver circuit of claim 1 , wherein the switching circuit includes at least one third transistor which is coupled to the first circuit node; the temporary current path being formed by the third transistor, which is configured to be temporarily activated in accordance with the control signal.

7. The bus driver circuit of claim 6 , wherein the at least one third transistor is composed of a plurality of transistor cells, or groups of transistor cells, having load current paths coupled in parallel to form the third transistor's load current path, which has an effective resistance;
the transistor cells, or groups of transistor cells, being configured to be sequentially switched or off, such that the effective resistance of the third transistor depends on the number of transistor cells, or groups of transistor cells, which are switched on.

8. The bus driver circuit of claim 7 , wherein each transistor cell, or each group of transistor cells, is configured to be switched on and off in accordance with a gate signal, each gate signal being generated based on a delayed version of the control signal.

9. The bus driver circuit of claim 1 , wherein the switching circuit comprises a transistor half-bridge having a low-side transistor and a high-side transistor;
the high-side transistor being coupled between the first circuit node and the second circuit node, which is a supply node;
the low-side transistor being coupled between the first circuit node and a further supply node supplied with a reference potential;
the high-side transistor being configured to be temporarily switched on to provide the temporary current path for discharging the bus capacitance during a transition period from a dominant to a recessive state.

10. The bus driver circuit of claim 9 ,
wherein both, the high-side transistor and the low-side transistor, comprise a plurality of transistor cells, or groups of parallel transistor cells, having load paths coupled in parallel and form a load path of the respective transistor; and
wherein the transistor cells, or groups of transistor cells, are configured to be sequentially switched or off, such that the effective resistance of the respective transistor depends on the number of transistor cells, or groups of transistor cells, which are switched on.

11. The bus driver circuit of claim 10 wherein the effective resistance is equal at a specific time instant during the transition from the dominant to the recessive state.

12. The bus driver circuit of claim 10 wherein the low-side transistor has a number of 2N transistor cells, or groups or parallel transistor cells, and the high-side transistor has a number of N transistor cells, or groups or parallel transistor cells; N being a positive integer number.

13. The bus driver circuit of claim 1 , wherein the switching circuit comprises a transistor H-bridge composed of a first transistor half bridge and a second transistor half bridge, each having a low-side transistor and a high-side transistor connected at a middle tap of the respective half-bridge.

14. The bus driver of claim 13 ,
wherein the first transistor half bridge and the second transistor half-bridge are coupled between a first supply node and a second supply node;
wherein the first supply node is the middle tap of the first transistor half bridge and the second supply node is the middle tap of the second transistor half bridge;
the high-side transistor of the first transistor half bridge and the low-side transistor of the second transistor half bridge being configured to be temporarily switched on to provide the temporary current path for discharging the bus capacitance during a transition period from a dominant to a recessive state.

15. The bus driver circuit of claim 14 ,
wherein the high-side transistors and the low-side transistors of the first transistor half bridge and the second transistor half-bridge, comprise a plurality of transistor cells, or groups of parallel transistor cells, having load paths coupled in parallel and form a load path of the respective transistor; and
wherein the transistor cells, or groups of transistor cells, are configured to be sequentially switched or off, such that the effective resistance of the respective transistor depends on the number of transistor cells, or groups of transistor cells, which are switched on.

16. The bus driver circuit of claim 15 ,
wherein, during a transition from the dominant to the recessive state, the high-side transistor of the first transistor half bridge and the low side transistor of the second transistor half bridge are synchronously switched off by sequentially switching off the transistor cells, or group of transistor cells, of the respective transistors; and
wherein, the low-side transistor of the first transistor half bridge and the high-side transistor of the second transistor half bridge are synchronously switched on and off by sequentially switching on and off the transistor cells, or group of transistor cells, of the respective transistors, such that at a specific time instant during the transition from the dominant to the recessive state the high side transistors and the low side transistors of the first transistor half bridge and second transistor half-bridge have substantially the same effective resistance.

17. The bus driver of claim 16 , wherein the low-side transistor of the first transistor half bridge and the high-side transistor of the second transistor half bridge are sequentially switched on before

Assignees

• Infineon Technologies Ag

Inventors

• Metzner Dieter
• Widerin Peter
• Astrom David

Classifications

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F2211/002

  Bus · CPC title