Gain stabilization

Patent metadata

Field	Value
Publication number	US-11870404-B2
Application number	US-202117320077-A
Country	US
Kind code	B2
Filing date	May 13, 2021
Priority date	May 13, 2021
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain-stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.

First claim

What is claimed is:

1. An apparatus comprising:
a pipeline analog-to-digital converter comprising:
at least two stages; and
at least one amplification circuit coupled between the at least two stages, the at least one amplification circuit comprising:
an amplifier having a gain that is based on a bias voltage and an amplification control signal; and
a gain-stabilization circuit coupled to the amplifier, the gain-stabilization circuit comprising:
a replica amplifier corresponding to the amplifier, the replica amplifier configured to have a replica gain that is based on the bias voltage and the amplification control signal,

the gain-stabilization circuit configured to adjust at least one of the bias voltage or the amplification control signal based on a difference between an input voltage and an output voltage of the replica amplifier.

2. The apparatus of claim 1 , wherein the gain-stabilization circuit is configured to substantially stabilize the gain of the amplifier and the replica gain of the replica amplifier based on the adjustment of at least one of the bias voltage or the amplification control signal.

3. The apparatus of claim 2 , wherein the gain-stabilization circuit is configured to substantially stabilize the gain of the amplifier and the replica gain of the replica amplifier to remain within a percentage threshold across a temperature range.

4. The apparatus of claim 2 , wherein:
the amplifier is coupled to a supply voltage node;
the replica amplifier is coupled to the supply voltage node; and
the gain-stabilization circuit is configured to substantially stabilize the gain of the amplifier and the replica gain of the replica amplifier to remain within a percentage threshold across a range associated with a supply voltage provided at the supply voltage node.

5. The apparatus of claim 1 , wherein:
the amplifier is configured to amplify an input signal;
a transconductance of the amplifier is based on the bias voltage; and
the gain of the amplifier and the replica gain of the replica amplifier are proportional to the transconductance.

6. The apparatus of claim 1 , wherein:
the amplifier is configured to amplify an input signal;
a pulsewidth of the amplification control signal controls a duration that the amplifier amplifies the input signal; and
the gain of the amplifier and the replica gain of the replica amplifier are proportional to the pulsewidth of the amplification control signal.

7. The apparatus of claim 1 , wherein the gain-stabilization circuit is configured to:
provide a calibration input voltage to the replica amplifier;
amplify the calibration input voltage using the replica amplifier to generate a calibration output voltage; and
determine the difference between the input voltage and the output voltage of the replica amplifier based on the calibration input voltage and the calibration output voltage.

8. The apparatus of claim 1 , wherein the gain-stabilization circuit is configured to:
increase a pulsewidth of the amplification control signal responsive to the difference between the input voltage and the output voltage of the replica amplifier indicating that the replica gain of the replica amplifier is lower than a target gain; or
decrease the pulsewidth of the amplification control signal responsive to the difference between the input voltage and the output voltage of the replica amplifier indicating that the replica gain of the replica amplifier is higher than the target gain.

9. The apparatus of claim 1 , wherein the gain-stabilization circuit is configured to:
adjust the bias voltage to increase a bias current responsive to the difference between the input voltage and the output voltage of the replica amplifier indicating that the replica gain of the replica amplifier is lower than a target gain; or
adjust the bias voltage to decrease a bias current responsive to the difference between the input voltage and the output voltage of the replica amplifier indicating that the replica gain of the replica amplifier is higher than the target gain.

10. The apparatus of claim 1 , wherein the gain-stabilization circuit comprises:
at least one of a bias voltage generator or an amplification control signal generator;
an input voltage generator coupled to an input of the replica amplifier; and
a gain-error correction circuit coupled to the input of the replica amplifier and an output of the replica amplifier, the gain-error correction circuit configured to provide at least one output to at least one of the bias voltage generator or the amplification control signal generator.

11. The apparatus of claim 10 , wherein the gain-error correction circuit comprises:
at least one scaler coupled to an input of the gain-error correction circuit;
at least one combiner coupled to an output of the at least one scaler; and
at least one integrator coupled to an output of the at least one combiner.

12. The apparatus of claim 1 , wherein the gain-stabilization circuit comprises:
at least one switched-capacitor digital-to-analog converter coupled to an input of the replica amplifier; and
at least one other switched-capacitive digital-to-analog converter coupled to an output of the replica amplifier.

13. The apparatus of claim 1 , wherein the gain-stabilization circuit is configured to compensate for at least one of a voltage offset or a flicker noise associated with the replica amplifier.

14. The apparatus of claim 1 , wherein the amplifier and the replica amplifier each comprise:
at least one input transistor configured to accept the input voltage at a gate terminal of the at least one input transistor;
at least one transistor configured to be biased by the amplification control signal, the at least one transistor coupled to a drain terminal of the at least one input transistor;
at least one other transistor coupled between a supply voltage and the at least one transistor, the at least one other transistor configured to be biased by a reset signal; and
at least one current source coupled to a source terminal of the at least one input transistor, the at least one current source configured to generate a current based on the bias voltage.

15. The apparatus of claim 1 , wherein an architecture of the replica amplifier is identical to an architecture of the amplifier.

16. The apparatus of claim 1 , wherein the replica amplifier represents a scaled version of the amplifier.

17. An apparatus comprising:
a pipeline analog-to-digital converter comprising:
at least two stages; and
at least one amplification circuit coupled between the at least two stages, the at least one amplification circuit comprising:
amplification means for providing a gain that is based on a bias voltage and an amplification control signal; and
gain-stabilization means for substantially stabilizing the gain of the amplification means, the gain-stabilization means comprising:
replication means for providing a replica gain that is based on the bias voltage and the amplification control signal; and
means for adjusting at least one of the bias voltage or the amplification control signal based on a difference between an input voltage and an output voltage of the replication means.

18. The apparatus of claim 17 , wherein:
the means for adjusting is configured to:
provide a calibration input voltage to the replication means; and
determine the difference between the input voltage and the output voltage of the replication means based on the calibration input voltage and a calibration output voltage; and

the replication means is conf

Assignees

• Qualcomm Inc

Inventors

• Yamamoto Kentaro
• Akhavan Aram
• Kiran Ganesh
• Sun Lei
• Dagher Elias
• Alladi Dinesh Jagannath

Classifications

• H03G3/3036 Primary

  in high-frequency amplifiers or in frequency-changers (H03G3/3052, H03G3/32, H03G3/34 take precedence) · CPC title

• H03F3/19

  with semiconductor devices only · CPC title

• H03F3/21

  with semiconductor devices only {(H03F3/245 takes precedence)} · CPC title

• H03M1/124

  Sampling or signal conditioning arrangements specially adapted for A/D converters · CPC title

• H03F2200/453

  Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit · CPC title