Constant VDS1 bias control for stacked transistor configuration

Patent metadata

Field	Value
Publication number	US-11870398-B2
Application number	US-202117475934-A
Country	US
Kind code	B2
Filing date	Sep 15, 2021
Priority date	Dec 28, 2012
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage. According to one aspect, the gate of the input transistor of the amplifier is biased with a fixed voltage whereas the gates of the other transistors of the amplifier are biased with variable voltages that are linear functions of the varying supply voltage. According to another aspect, the linear functions are such that the variable voltages coincide with the fixed voltage at a value of the varying supply voltage for which the input transistor is at the edge of triode. According to another aspect, biasing of the stacked transistors is such that, while the supply voltage varies, the drain-to-source voltage of the input transistor is maintained to a fixed value whereas the drain-to-source voltages of all other transistors are equal to one another.

First claim

The invention claimed is:

1. A circuital arrangement comprising:
an amplifier comprising an input transistor and a plurality of cascode transistors comprising a first cascode transistor coupled to the input transistor and remaining one or more cascode transistors;
a biasing circuit comprising:
a plurality of series-connected resistors coupled between a varying supply voltage to the amplifier and a reference ground, the plurality of series-connected resistors coupled to one another through a plurality of nodes; and
a substantially fixed reference supply voltage coupled to a first node of the plurality of nodes,

wherein:
a gate of the first cascode transistor is coupled to a respective node of the plurality of nodes that is arranged between the first node and the reference ground, and
gates of the remaining one or more cascode transistors are coupled to respective nodes of the plurality of nodes that are arranged between the varying supply voltage and the first node.

2. The circuital arrangement according to claim 1 , further comprising:
a plurality of resistors coupled between gates of respective transistors of the plurality of cascode transistors and the respective nodes.

3. The circuital arrangement according to claim 1 , further comprising:
a plurality of gate capacitors connected between gates of respective transistors of the plurality of cascode transistors and the reference ground,
wherein each gate capacitor of the plurality of gate capacitors is configured to allow a voltage at the gate of the respective transistor to vary along with a radio frequency (RF) voltage at a drain of the respective transistor.

4. The circuital arrangement according to claim 1 , wherein:
the plurality of series-connected resistors comprises at least one resistor coupled between the first node and the respective node coupled to the gate of the first cascode transistor.

5. The circuital arrangement according to claim 1 , wherein:
the plurality of series-connected resistors comprises at least one resistor coupled between the first node and any of the respective nodes coupled to the gates of the remaining one or more cascode transistors.

6. The circuital arrangement according to claim 1 , wherein:
the respective node of the plurality of nodes coupled to the gate of the first cascode transistor is configured to provide a substantially fixed bias voltage, and
the respective nodes of the plurality of nodes coupled to the gates of the remaining one or more cascode transistors are configured to provide respective one or more variable bias voltages based on the varying supply voltage.

7. The circuital arrangement according to claim 6 , wherein:
the respective one or more variable bias voltages control respective one or more drain-to-source voltages of the remaining one or more cascode transistors to be substantially equal.

8. The circuital arrangement according to claim 6 , wherein:
the substantially fixed bias voltage is configured to maintain a substantially constant drain voltage of the input transistor.

9. The circuital arrangement according to claim 1 , wherein the variable supply voltage varies in a range from 1 volt to 5 volts.

10. The circuital arrangement according to claim 1 , wherein the input transistor and the plurality of cascode transistors are metal-oxide-semiconductor (MOS) field effect transistors (FETs), or complementary metal-oxide-semiconductor (CMOS) field effect transistors (FETs).

11. The circuital arrangement according to claim 10 , wherein said transistors are fabricated using one of: a) silicon-on-insulator (SOI) technology, and b) silicon-on-sapphire technology (SOS).

12. A circuital arrangement comprising:
an amplifier comprising an input transistor and a plurality of cascode transistors comprising a first cascode transistor coupled to the input transistor and remaining one or more cascode transistors;
a biasing circuit comprising:
a first plurality of series-connected resistors coupled between a substantially fixed reference voltage and a reference ground, the first plurality of series-connected resistors coupled to one another through one or more first nodes;
a second plurality of series-connected resistors coupled between a varying supply voltage to the amplifier and a reference ground, the second plurality of series-connected resistors coupled to one another through one or more second nodes;

wherein:
a gate of the first cascode transistor is coupled to a respective node of the one or more first nodes, and
gates of the remaining one or more cascode transistors are coupled to respective nodes of the one or more second nodes.

13. The circuital arrangement according to claim 12 , further comprising:
a plurality of resistors coupled between gates of respective transistors of the plurality of cascode transistors and the respective nodes.

14. The circuital arrangement according to claim 12 , further comprising:
a plurality of gate capacitors connected between gates of respective transistors of the plurality of cascode transistors and the reference ground,
wherein each gate capacitor of the plurality of gate capacitors is configured to allow a voltage at the gate of the respective transistor to vary along with a radio frequency (RF) voltage at a drain of the respective transistor.

15. A method for biasing an amplifier, the method comprising:
providing an amplifier comprising an input transistor and a plurality of cascode transistors comprising a first cascode transistor coupled to the input transistor and remaining one or more cascode transistors;
coupling a plurality of series-connected resistors between a varying supply voltage to the amplifier and a reference ground, thereby obtaining a plurality of nodes of the series-connected resistors;
coupling a substantially fixed reference supply voltage to a first node of the plurality of nodes,
coupling a gate of the first cascode transistor to a respective node of the plurality of nodes that is arranged between the first node and the reference ground, and
coupling gates of the remaining one or more cascode transistors to respective nodes of the plurality of nodes that are arranged between the varying supply voltage and the first node.

16. The method according to claim 15 , the method further comprising:
coupling a plurality of resistors between gates of respective transistors of the plurality of cascode transistors and the respective nodes.

17. The method according to claim 15 , the method further comprising:
connecting a plurality of gate capacitors between gates of respective transistors of the plurality of cascode transistors and the reference ground; and
based on the connecting, allowing respective voltages at the gates of the respective transistors to vary along with respective radio frequency (RF) voltages at drains of the respective transistors.

Assignees

• Psemi Corp

Inventors

• Ranta Tero Tapio
• Murphy Christopher C
• Dykstra Jeffrey A

Classifications

• H03F1/22 Primary

  by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively · CPC title

• H03F1/0227

  using supply converters · CPC title

• H03F1/223

  with MOSFET's · CPC title

• H03F1/301

  in MOSFET amplifiers (H03F1/303, H03F1/305, H03F1/308 take precedence) · CPC title

• H03F1/3205

  in field-effect transistor amplifiers · CPC title