Method for forming a semiconductor device

Patent metadata

Field	Value
Publication number	US-11869836-B2
Application number	US-202318105955-A
Country	US
Kind code	B2
Filing date	Feb 6, 2023
Priority date	Nov 28, 2019
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.

First claim

What is claimed is:

1. A method for forming a semiconductor device, the method comprising:
forming an interlayer insulating layer on a substrate;
forming a contact hole penetrating the interlayer insulating layer;
forming a lower pattern and a barrier pattern in the contact hole such that the barrier pattern is between the lower pattern and the interlayer insulating layer;
forming an upper insulating layer on the interlayer insulating layer such that the upper insulating layer covers topmost surfaces of the lower pattern and the barrier pattern;
forming a trench in the upper insulating layer such that the trench exposes the topmost surfaces of the lower pattern and the barrier pattern;
forming a recess region in the interlayer insulating layer by recessing the topmost surfaces of the lower pattern and the barrier pattern; and
forming an upper pattern filing the recess region,
wherein the upper pattern includes a protrusion protruding upwardly from a top surface of the interlayer insulating layer.

2. The method as claimed in claim 1 , wherein the protrusion has a width in a direction parallel to a top surface of the substrate, and a width of a lower region of the protrusion is greater than a width of an upper region of the protrusion.

3. The method as claimed in claim 2 , wherein the lower region of the protrusion extends on the top surface of the interlayer insulating layer.

4. The method as claimed in claim 2 , wherein the width of the protrusion becomes narrower from a bottom of the protrusion toward a top of the protrusion.

5. The method as claimed in claim 1 , wherein:
the upper pattern includes a first metal, and
the lower pattern includes a second metal different from the first metal.

6. The method as claimed in claim 1 , wherein the upper pattern and the lower pattern include a same metal.

7. The method as claimed in claim 1 , wherein forming the lower pattern and the barrier pattern includes:
forming a barrier layer filling a portion of the contact hole on the interlayer insulating layer,
forming a lower layer filling a remaining portion of the contact hole on the barrier layer, and
planarizing the lower layer and the barrier layer until the top surface of the interlayer insulating layer is exposed.

8. The method as claimed in claim 1 , wherein, after forming the recess region, the recessed topmost surface of the barrier pattern is at a lower height from the substrate than or substantially the same height as the recessed topmost surface of the lower pattern.

9. The method as claimed in claim 8 , wherein the upper pattern covers the recessed topmost surface of the barrier pattern and the recessed topmost surface of the lower pattern.

10. The method as claimed in claim 1 , wherein forming, the upper pattern includes performing a selective growth process using the lower pattern and the barrier pattern, which are exposed by the recess region, as a seed.

11. The method as claimed in claim 1 , further comprising forming a conductive line on the interlayer insulating layer and in the trench,
wherein the lower pattern, the barrier pattern, and the upper pattern constitute a contact plug.

12. The method as claimed in claim 11 , wherein:
the conductive line includes:
a line pattern extending in one direction on the interlayer insulating layer, and
a line barrier pattern between the line pattern and the interlayer insulating layer,

a topmost surface of the protrusion is at a higher height from the substrate than the top surface of the interlayer insulating layer, and
the line barrier pattern extends from the top surface of the interlayer insulating layer onto the topmost surface of the protrusion.

13. A method for forming a semiconductor device, the method comprising:
forming an active fin on a substrate such that the active fin includes a plurality of semiconductor patterns spaced apart from each other in a first direction perpendicular to a top surface of the substrate;
forming a gate electrode on the active fin such that the gate electrode covers a topmost surface of the active fin and extends between the plurality of semiconductor patterns;
forming an interlayer insulating layer on the gate electrode;
forming a conductive line on the interlayer insulating layer; and
forming a contact plug penetrating the interlayer insulating layer such that the contact plug is connected to the conductive line,
wherein:
the contact plug includes a protrusion protruding upwardly from a top surface of the interlayer insulating layer, and
the protrusion has a width in a second direction parallel to the top surface of the substrate, and a width of a lower region of the protrusion is greater than a width of an upper region of the protrusion.

14. The method as claimed in claim 13 , wherein the lower region of the protrusion extends on the top surface of the interlayer insulating layer.

15. The method as claimed in claim 13 , wherein the width of the protrusion becomes narrower from a bottom of the protrusion toward a top of the protrusion.

16. The method as claimed in claim 13 , wherein:
forming the contact plug includes:
forming a contact hole penetrating the interlayer insulating layer,
forming a lower pattern and a barrier pattern in the contact hole such that the barrier pattern is between the lower pattern and the interlayer insulating layer,
forming a recess region in the interlayer insulating layer by recessing topmost surfaces of the lower pattern and the barrier pattern, and
forming an upper pattern filing the recess region, and

the upper pattern includes the protrusion.

17. The method as claimed in claim 16 , wherein:
the upper pattern includes a first metal, and
the lower pattern includes a second metal different from the first metal.

18. The method as claimed in claim 16 , wherein the upper pattern and the lower pattern include a same metal.

19. The method as claimed in claim 16 , wherein, after forming the recess region, the recessed topmost surface of the barrier pattern is at a lower height from the substrate than or substantially the same height as the recessed topmost surface of the lower pattern.

20. The method as claimed in claim 13 , further comprising;
forming source/drain patterns spaced apart from each other in the second direction with the active fin therebetween; and
forming a lower contact plug at a side of the gate electrode,
wherein the lower contact plug is electrically connected to a corresponding one of the source/drain patterns, and
wherein the contact plug is electrically connected to the lower contact plug.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Seo Donghee
• Lee Heonbok
• Kim Tae-Yeol
• Kim Daeyong
• Lee Dohyun

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title