Thermal interface structures for integrated circuit packages

US11869824B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11869824-B2
Application numberUS-201916672858-A
CountryUS
Kind codeB2
Filing dateNov 4, 2019
Priority dateNov 4, 2019
Publication dateJan 9, 2024
Grant dateJan 9, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A thermal interface structure may be formed comprising a thermally conductive substrate having a first surface and an opposing second surface, a first liquid metal layer on the first surface of the thermally conductive substrate, and a second liquid metal layer on the second surface of the thermally conductive substrate. The thermal interface structure may be used in an integrated circuit assembly or package between at least one integrated circuit device and a heat dissipation device.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus, comprising: at least one integrated circuit device; a heat dissipation device; and a thermal interface structure thermally connecting the at least one integrated circuit device and the heat dissipation device, wherein the thermal interface structure comprises a thermally conductive substrate having a first surface and an opposing second surface, a first liquid metal layer between the at least one integrated circuit device and the first surface of the thermally conductive substrate, and a second liquid metal layer between the heat dissipation device and the second surface of the thermally conductive substrate, wherein the thermally conductive substrate comprises at least one opening extending from the first surface of the thermally conductive substrate to the second surface of the thermally conductive substrate, and wherein at least a portion of at least one of the first liquid metal layer and the second liquid metal layer extends into the at least one opening. 2. The apparatus of claim 1 , wherein at least one of the first liquid metal layer and the second liquid metal layer comprises an alloy of gallium, indium, and tin. 3. The apparatus of claim 1 , wherein the thermally conductive substrate is selected from the group consisting of a metal substrate, a ceramic substrate, and a gap pad. 4. The apparatus of claim 1 , wherein the thermally conductive substrate comprises an amorphous metal substrate. 5. The apparatus of claim 1 , wherein the thermally conductive substrate comprises a refractory metal substrate. 6. The apparatus of claim 1 , further comprising a corrosion barrier layer between the heat dissipation device and the thermal interface structure. 7. The apparatus of claim 1 , further comprising an electronic substrate, wherein the at least one integrated circuit device is electrically attached to the electronic substrate. 8. The apparatus of claim 7 , wherein the heat dissipation device is attached to the electronic substrate. 9. The apparatus of claim 1 , further comprising: a board; and an integrated circuit assembly electrically attached to the board, wherein the integrated circuit assembly comprises the integrated circuit device, the heat dissipation device, and the thermal interface structure. 10. An apparatus, comprising: an integrated circuit device; a heat dissipation device; and a thermal interface structure thermally coupling the integrated circuit device and the heat dissipation device, wherein the thermal interface structure comprises a substrate having a first surface and an opposing second surface, a first liquid metal layer between the integrated circuit device and the first surface, and a second liquid metal layer between the heat dissipation device and the second surface, wherein the substrate comprises an opening extending from the first surface to the second surface, and wherein at least a portion of at least one of the first liquid metal layer and the second liquid metal layer extends into the opening. 11. The apparatus of claim 10 , wherein at least one of the first liquid metal layer and the second liquid metal layer comprises an alloy of gallium, indium, and tin. 12. The apparatus of claim 10 , wherein the substrate is selected from the group consisting of a metal substrate, a ceramic substrate, and a gap pad. 13. The apparatus of claim 10 , wherein the substrate comprises an amorphous metal substrate. 14. The apparatus of claim 10 , wherein the substrate comprises a refractory metal substrate. 15. The apparatus of claim 10 , further comprising a corrosion barrier layer between the heat dissipation device and the thermal interface structure. 16. The apparatus of claim 10 , further comprising an electronic substrate, wherein the integrated circuit device is electrically attached to the electronic substrate. 17. The apparatus of claim 10 , further comprising: a board; and an integrated circuit assembly electrically attached to the board, wherein the integrated circuit assembly comprises the integrated circuit device, the heat dissipation device, and the thermal interface structure. 18. An apparatus, comprising: an integrated circuit device; a heat dissipation device; and a thermal interface structure thermally coupling the integrated circuit device and the heat dissipation device, wherein the thermal interface structure comprises a substrate having a first surface and an opposing second surface, a first liquid metal layer between the integrated circuit device and the first surface, and a second liquid metal layer between the heat dissipation device and the second surface, wherein the first liquid metal layer and the second liquid metal layer are liquid at a temperature of 25 degrees Celsius, and wherein the substrate comprises an opening extending from the first surface to the second surface, and wherein at least a portion of at least one of the first liquid metal layer and the second liquid metal layer extends into the opening. 19. The apparatus of claim 18 , wherein at least one of the first liquid metal layer and the second liquid metal layer comprises an alloy of gallium, indium, and tin. 20. The apparatus of claim 18 , wherein the substrate is selected from the group consisting of a metal substrate, a ceramic substrate, and a gap pad. 21. The apparatus of claim 18 , wherein the substrate comprises an amorphous metal substrate. 22. The apparatus of claim 18 , wherein the substrate comprises a refractory metal substrate. 23. The apparatus of claim 18 , further comprising a corrosion barrier layer between the heat dissipation device and the thermal interface structure. 24. The apparatus of claim 18 , further comprising an electronic substrate, wherein the integrated circuit device is electrically attached to the electronic substrate. 25. The apparatus of claim 18 , further comprising: a board; and an integrated circuit assembly electrically attached to the board, wherein the integrated circuit assembly comprises the integrated circuit device, the heat dissipation device, and the thermal interface structure.

Assignees

Inventors

Classifications

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • changes in materials · CPC title

  • Eutectic alloys · CPC title

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What does patent US11869824B2 cover?
A thermal interface structure may be formed comprising a thermally conductive substrate having a first surface and an opposing second surface, a first liquid metal layer on the first surface of the thermally conductive substrate, and a second liquid metal layer on the second surface of the thermally conductive substrate. The thermal interface structure may be used in an integrated circuit assem…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W40/255. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 09 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).