Optimizating semiconductor binning by feed-forward process adjustment

Patent metadata

Field	Value
Publication number	US-11869783-B2
Application number	US-202117244084-A
Country	US
Kind code	B2
Filing date	Apr 29, 2021
Priority date	Oct 24, 2017
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target sorting bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.

First claim

What is claimed is:

1. A method for generating a machine learning model for improving performance levels of semiconductor devices during fabrication, the method comprising:
determining, by one or more processors, a first set of correlations between process parameters applied to a metallization layer process of semiconductor device fabrication and data from measurement and test operations performed subsequent to the metallization layer of the semiconductor devices, for a plurality of metallization layers performed during fabrication of a plurality of semiconductor devices;
determining, by one or more processors, a second set of correlations between the data from measurement and test operations performed subsequent to the metallization layer of the semiconductor devices and predicted performance level of the semiconductor devices;
generating a machine learning model, based on the first set of correlations and the second set of correlations; and
training the machine learning model to:
determine an initial sorting bin, a target soring bin, and a current sorting bin of a first semiconductor device, and
determine adjustments to process parameters of a subsequent metallization layer that improve the performance levels of the first semiconductor device by compensating for performance-reducing conditions detected by prior process measurement and testing operations.

2. The method of claim 1 , wherein determining the initial sorting bin and determining the current sorting bin of the first semiconductor device includes projecting a performance level of the first semiconductor device in which the performance level includes measurement of a combination from a group of: resistance and capacitance, critical path delay, processing speed, frequency, reliability, power consumption, and special featured functions.

3. The method of claim 1 , wherein adjustments to process parameters of subsequent metallization layers are determined based on the remaining number of metallization layers for the first semiconductor device, an amount of compensating improvement attainable from cumulative adjustments to process parameters of a metallization layer, and a determined amount of performance improvement to meet performance criteria of the target sorting bin.

4. The method of claim 1 , wherein the machine learning model determines the highest performance target sorting bin attainable by applying adjustments to subsequent metallization layers for the first semiconductor device, and wherein the subsequent metallization layer is one of multiple metallization layers performed in fabrication of the first semiconductor device.

5. The method of claim 1 , wherein an adjustment to subsequent metallization layer process parameters includes an adjustment to a design of the first semiconductor device.

6. The method of claim 1 , wherein the measurement and testing of performance data includes one or a combination from a group consisting of: mechanical measurements, optical measurements, electrical measurements, manual testing, optical testing, and electrical testing.

7. The method of claim 1 , wherein the determination of the initial sorting bin, the target sorting bin, and a current sorting bin of the first semiconductor device, as well as the determination of the adjustments to process parameters of a subsequent metallization layer that are predicted to improve the physical and electrical performance levels of the first semiconductor device, are based on the first set of correlations, the second set of correlations, and the determined current sorting bin of the first semiconductor, and by performing supervised learning techniques on the machine learning model utilizing the metallization layer process parameter data, data from measurement and test operations performed, and performance level data obtained from a plurality of wafers during fabrication of multiple semiconductor devices.

8. The method of claim 1 , wherein data applied to the machine learning model during supervised learning techniques includes empirical results obtained by intentional process parameter variation during chip metallization processes, the resulting measurement and testing data, and the known projections of binning designation based on the received measurement and testing data of the plurality of semiconductor devices.

9. A method for improving a performance level of a semiconductor device, the method comprising:
determining, by one or more processors, a predicted sorting bin of a semiconductor device, based on data from measurement and test operations performed on the semiconductor device subsequent to a current metallization layer;
determining, by one or more processors, a target sorting bin for the semiconductor device, based on the data from measurement and test operations performed on the semiconductor device and a machine learning model that determines an attainable performance level improvement based on adjustments to process parameters of subsequent metallization layers of the semiconductor device;
identifying, by one or more processors, process parameter adjustments to the subsequent metallization layers of the semiconductor device; and
applying, by one or more processors, the adjustments to the process parameters of the subsequent metallization layer processes of the semiconductor device.

10. The method of claim 9 , wherein the adjustments to the process parameters of the subsequent metallization layer processes are determined by the machine learning model and, wherein cumulative adjustment outputs across multiple metallization layers provides performance improvement of the semiconductor device to at least meet performance criteria of the target sorting bin for the semiconductor device.

11. The method of claim 9 , wherein a feed-forward mechanism transmits a notification including the process parameter adjustments for respective processes of a subsequent metallization layer of the semiconductor device as user awareness for manual setup.

12. The method of claim 9 , wherein a feed-forward mechanism automatically transmits the adjustments for the process parameters of the subsequent metallization layers of the semiconductor device to respective processes of the subsequent metallization layers of the semiconductor device.

13. The method of claim 9 , wherein the adjustments to process parameters of the subsequent metallization layers include adding additional metallization layers for the semiconductor device.

14. The method of claim 9 , wherein the adjustments to the process parameters includes adjustments to design patterns of the semiconductor device.

15. The method of claim 9 , wherein a feed-forward mechanism continuously re-trains the machine learning model by program instruction to transmit to the machine learning model adjustments for the process parameters of the one or more subsequent metallization layers, performance level testing data of the semiconductor device, and sorting bin designations associated with the semiconductor device.

16. The method of claim 9 , wherein the determination of a predicted current sorting bin and the target sorting bin is performed prior to each metallization layer.

17. A computer system for generating a machine learning model for improving performance levels of semiconductor devices during fabrication, the computer system comprising:
one or more computer processors,
one or more computer readable storage media,
program instructions stored on the computer readable storage media for execution by at least one of the one or more processors, the program instructions comprising:
program instructions to determi

Assignees

• IBM

Inventors

• Briggs Benjamin D
• Clevenger Lawrence A
• Lanzillo Nicholas A
• Rizzolo Michael
• Standaert Theodorus E
• Stathis James

Classifications

• H10P72/0611 Primary

  Sorting devices · CPC title

• H01L21/67271 Primary

  Electricity · mapped topic

• G06N5/04

  Inference or reasoning models · CPC title

• G06N20/00 Primary

  Machine learning · CPC title

• G06N5/046

  Forward inferencing; Production systems · CPC title