Sense amplifier, memory and method for controlling sense amplifier

Patent metadata

Field	Value
Publication number	US-11869624-B2
Application number	US-202117472805-A
Country	US
Kind code	B2
Filing date	Sep 13, 2021
Priority date	Jul 27, 2020
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

A sense amplifier includes: an amplification circuit, configured to read data of a memory cell on a first bit line or a second bit line; and a first offset voltage storage cell and a second offset voltage storage cell, respectively and electrically connected to the amplification circuit, wherein in a case where the data in the memory cell on the first bit line is read, in an offset elimination stage of the sense amplifier, the sense amplifier is configured to store an offset voltage of the sense amplifier in the first offset voltage storage cell; and in a case where the data in the memory cell on the second bit line is read, in the offset elimination stage of the sense amplifier, the sense amplifier is configured to store the offset voltage of the sense amplifier in the second offset voltage storage cell.

First claim

The invention claimed is:

1. A sense amplifier, comprising:
an amplification circuit, configured to read data of a memory cell on a first bit line or a second bit line; and
a first offset voltage storage cell and a second offset voltage storage cell, respectively and electrically connected to the amplification circuit,
wherein in a case where the data in the memory cell on the first bit line is read, in an offset elimination stage of the sense amplifier, the sense amplifier is configured to store an offset voltage of the sense amplifier in the first offset voltage storage cell; and in a case where the data in the memory cell on the second bit line is read, in the offset elimination stage of the sense amplifier, the sense amplifier is configured to store the offset voltage of the sense amplifier in the second offset voltage storage cell,
wherein the amplification circuit comprises:
a first Positive channel Metal Oxide Semiconductor (PMOS) transistor;
a second PMOS transistor, a source of the second PMOS transistor being connected to a source of the first PMOS transistor;
a first Negative channel Metal Oxide Semiconductor (NMOS) transistor, a drain of the first NMOS transistor being connected to a drain of the first PMOS transistor; and
a second NMOS transistor, a drain of the second NMOS transistor being connected to a drain of the second PMOS transistor, and a source of the second NMOS transistor being connected to a source of the first NMOS transistor,

wherein a first end of the first offset voltage storage cell is connected to the drain of the first NMOS transistor, and a second end of the first offset voltage storage cell is connected to a gate of the second NMOS transistor,
wherein a first end of the second offset voltage storage cell is connected to a gate of the first NMOS transistor, and a second end of the second offset voltage storage cell is connected to the drain of the second NMOS transistor, and
wherein in the offset elimination stage of the sense amplifier, the first PMOS transistor and the second PMOS transistor are configured as a current mirror, and the first NMOS transistor and the second NMOS transistor are both configured to be in a diode connection mode.

2. The sense amplifier of claim 1 , wherein the drain of the first PMOS transistor and the drain of the first NMOS transistor are connected to a first node, and the drain of the second PMOS transistor and the drain of the second NMOS transistor are connected to a second node; and the sense amplifier further comprises:
a first switch, a first end of the first switch being connected to the first node, and a second end of the first switch being connected to the gate of the first NMOS transistor;
a second switch, a first end of the second switch being connected to the second node, and a second end of the second switch being connected to the gate of the second NMOS transistor; and
a third switch, a first end of the third switch being connected to a gate of the first PMOS transistor, and a second end of the third switch being connected to a gate of the second PMOS transistor,
wherein in the offset elimination stage of the sense amplifier, the first switch, the second switch and the third switch are all in a closed state.

3. The sense amplifier of claim 2 , further comprising:
a pull-up circuit, configured to control a connection state of the source of the first PMOS transistor with a power voltage in response to a pull-up control signal; and
a pull-down circuit, configured to, in response to a pull-down control signal, control whether the source of the first NMOS transistor is grounded,
wherein in the offset elimination stage of the sense amplifier, the source of the first PMOS transistor is connected to the power voltage, and the source of the first NMOS transistor is grounded.

4. The sense amplifier of claim 3 , further comprising:
a fourth switch, a first end of the fourth switch being connected to the gate of the first NMOS transistor, and a second end of the fourth switch being connected to the second node;
a fifth switch, a first end of the fifth switch being connected to the gate of the second PMOS transistor, and a second end of the fifth switch being connected to the gate of the second NMOS transistor;
a sixth switch, a first end of the sixth switch being connected to the gate of the second NMOS transistor, and a second end of the sixth switch being connected to the first node; and
a seventh switch, a first end of the seventh switch being connected to the gate of the first PMOS transistor, and a second end of the seventh switch being connected to the gate of the first NMOS transistor.

5. The sense amplifier of claim 4 , wherein in the case where the data in the memory cell on the first bit line is read, in the offset elimination stage of the sense amplifier, the fifth switch is open, and the seventh switch is closed; and
in the case where the data in the memory cell on the second bit line is read, in the offset elimination stage of the sense amplifier, the fifth switch is closed, and the seventh switch is open.

6. The sense amplifier of claim 5 , further comprising:
an eighth switch, a first end of the eighth switch being connected to the first bit line, and a second end of the eighth switch being connected to the first node; and
a ninth switch, a first end of the ninth switch being connected to the second bit line, and a second end of the ninth switch being connected to the second node,
wherein in the offset elimination stage of the sense amplifier, both the eighth switch and the ninth switch are open.

7. The sense amplifier of claim 6 , wherein after the offset elimination stage of the sense amplifier, a memory cell on the first bit line or a memory cell on the second bit line is enabled, the first switch is open, and the eighth switch and the ninth switch are closed, to input a voltage difference between the first bit line and the second bit line to the sense amplifier.

8. The sense amplifier of claim 7 , wherein in a case where the voltage difference between the first bit line and the second bit line is input to the sense amplifier, the source of the first PMOS transistor is connected to the power voltage, and the source of the first NMOS transistor is grounded, to amplify the voltage difference.

9. The sense amplifier of claim 5 , further comprising:
a precharge circuit, configured to precharge the first bit line and the second bit line when the sense amplifier is in a precharge stage.

10. The sense amplifier of claim 9 , wherein the precharge stage and the offset elimination stage are configured as being performed concurrently.

11. A memory, comprising a sense amplifier, wherein the sense amplifier comprises:
an amplification circuit, configured to read data of a memory cell on a first bit line or a second bit line; and
a first offset voltage storage cell and a second offset voltage storage cell, respectively and electrically connected to the amplification circuit,
wherein in a case where the data in the memory cell on the first bit line is read, in an offset elimination stage of the sense amplifier, the sense amplifier is configured to store an offset voltage of the sense amplifier in the first offset voltage storage cell; and in a case where the data in the memory cell on the second bit line is read, in the offset elimination stage of the sense amplifier, the sense amplifier is configured to store the offset voltage of the sense amplifier in the second offset voltage storage cell,
wherein the amplification circuit comprises:
a first Positive channel Metal Oxide Semiconductor (PMOS) transistor;
a second PMOS transistor, a source of the second PMOS transistor being connected to a

Assignees

• Univ Anhui
• Changxin Memory Tech Inc

Inventors

• Lu Wenjuan
• Zhao Yangkuo
• He Jun
• Li Xin
• Ying Zhan
• Cao Kanyu
• Peng Chunyu
• Wu Xiulong
• Lin Zhiting
• Chen Junning

Classifications

• G11C7/08 Primary

  Control thereof · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title