Bit line sense amplifier circuit capable of reducing offset voltage

Patent metadata

Field	Value
Publication number	US-10950279-B2
Application number	US-201916545805-A
Country	US
Kind code	B2
Filing date	Aug 20, 2019
Priority date	Aug 28, 2018
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

A BLSA circuit includes a first inverter disposed between a first sensing node and a second inner bit line, a second inverter disposed between a second sensing node and a first inner bit line, a first capacitor disposed between a first bit line and the first sensing node, a second capacitor disposed between a second bit line and the second sensing node, a first offset canceling switch for electrically coupling the first inner bit line with the second sensing node during an offset canceling operation, a second offset canceling switch for electrically coupling the second inner bit line with the first sensing node during the offset canceling operation, a first isolation switch for electrically coupling the first bit line with the first inner bit line, and a second isolation switch for electrically coupling the second bit line with the second inner bit line.

First claim

What is claimed is:

1. A bit line sense amplifier (BLSA) circuit comprising:
a first inverter having an input terminal coupled to a first sensing node and an output terminal coupled to a second inner bit line;
a second inverter having an input terminal coupled to a second sensing node and an output terminal coupled to a first inner bit line;
a first capacitor coupled to and disposed between a first bit line and the first sensing node;
a second capacitor coupled to and disposed between a second bit line and the second sensing node;
a first offset canceling switch suitable for electrically coupling the first inner bit line with the second sensing node during an offset canceling operation;
a second offset canceling switch suitable for electrically coupling the second inner bit line with the first sensing node during the offset canceling operation;
a first isolation switch suitable for electrically coupling the first bit line with the first inner bit line; and
a second isolation switch suitable for electrically coupling the second bit line with the second inner bit line,
wherein the BLSA circuit sequentially performs a precharge operation, the offset canceling operation, a charge sharing operation, and an amplification operation, and
wherein during the offset canceling operation, the first and second inverters are activated, the first and second offset canceling switches are turned on, and the first and second isolation switches are turned off.

2. The BLSA circuit of claim 1 , wherein during the precharge operation, the first inner bit line, the second inner bit line, the first bit line, the second bit line, the first sensing node, and the second sensing node are precharged with a same voltage level.

3. The BLSA circuit of claim 1 , wherein during the precharge operation, the first and second inverters are deactivated, and the first and second offset canceling switches and the first and second isolation switches are turned on.

4. The BLSA circuit of claim 3 , wherein during the precharge operation, a bit line precharge voltage is applied to pull-up voltage supply terminals and pull-down voltage supply terminals of the first and second inverters, and applied to the first and second inner bit lines.

5. The BLSA circuit of claim 1 , wherein the BLSA circuit is driven by a first power supply voltage during the offset canceling operation and a first time period of a pre-amplification operation, and driven by a second power supply voltage during a second time period of the amplification operation, the second time period following the first time period, the first power supply voltage having a higher voltage level than the second power supply voltage.

6. A bit line sense amplifier (BLSA) circuit comprising:
a first inverter having an input terminal coupled to a first sensing node and an output terminal coupled to a second inner bit line;
a second inverter having an input terminal coupled to a second sensing node and an output terminal coupled to a first inner bit line;
a first capacitor coupled to and disposed between a first bit line and the first sensing node;
a second capacitor coupled to and disposed between a second bit line and the second sensing node;
a first offset canceling switch suitable for electrically coupling the first inner bit line with the second sensing node during an offset canceling operation;
a second offset canceling switch suitable for electrically coupling the second inner bit line with the first sensing node during the offset canceling operation;
a first isolation switch suitable for electrically coupling the first bit line with the first inner bit line; and
a second isolation switch suitable for electrically coupling the second bit line with the second inner bit line,
wherein the BLSA circuit sequentially performs a precharge operation, the offset canceling operation, a charge sharing operation, and an amplification operation, and
wherein during the charge sharing operation, the first and second inverters are activated, and charge sharing is performed between a selected memory cell and one of the first and second bit lines to which the selected memory cell is coupled, when the first and second offset canceling switches and the first and second isolation switches are being turned off.

7. A bit line sense amplifier (BLSA) circuit comprising:
a first inverter having an input terminal coupled to a first sensing node and an output terminal coupled to a second inner bit line;
a second inverter having an input terminal coupled to a second sensing node and an output terminal coupled to a first inner bit line;
a first capacitor coupled to and disposed between a first bit line and the first sensing node;
a second capacitor coupled to and disposed between a second bit line and the second sensing node;
a first offset canceling switch suitable for electrically coupling the first inner bit line with the second sensing node during an offset canceling operation;
a second offset canceling switch suitable for electrically coupling the second inner bit line with the first sensing node during the offset canceling operation;
a first isolation switch suitable for electrically coupling the first bit line with the first inner bit line; and
a second isolation switch suitable for electrically coupling the second bit line with the second inner bit line,
wherein the BLSA circuit sequentially performs a precharge operation, the offset canceling operation, a charge sharing operation, and an amplification operation, and
wherein during the amplification operation, the first and second inverters are activated, the first and second isolation switches are turned on, and the first and second offset canceling switches are turned off.

8. A bit line sense amplifier (BLSA) circuit comprising:
a first inverter having an input terminal coupled to a first sensing node and an output terminal coupled to a second inner bit line;
a second inverter having an input terminal coupled to a second sensing node and an output terminal coupled to a first inner bit line;
a first capacitor coupled to and disposed between a first bit line and the first sensing node;
a second capacitor coupled to and disposed between a second bit line and the second sensing node;
a first offset canceling switch suitable for electrically coupling the first inner bit line with the second sensing node during an offset canceling operation;
a second offset canceling switch suitable for electrically coupling the second inner bit line with the first sensing node during the offset canceling operation;
a first isolation switch suitable for electrically coupling the first bit line with the first inner bit line; and
a second isolation switch suitable for electrically coupling the second bit line with the second inner bit line,
wherein the BLSA circuit sequentially performs a precharge operation, the offset canceling operation, a charge sharing operation, a pre-amplification operation, and an amplification operation.

9. The BLSA circuit of claim 8 , wherein during the precharge operation, the first inner bit line, the second inner bit line, the first bit line, the second bit line, the first sensing node, and the second sensing node are precharged with a same voltage level.

10. The BLSA circuit of claim 8 , wherein during the precharge operation, the first and second inverters are deactivated, and the first and second offset canceling switches and the first and second isolation switches are turned on.

11. The BLSA circuit of claim 10 , wherein during the precharge operation, a bit line precharge voltage is applied to pull-up voltage supply terminals and pull-down voltage supply terminals of the first and second inverters, an

Assignees

• Sk Hynix Inc
• Seoul Nat Univ R&Db Foundation

Inventors

• Jeong Deog-Kyoon
• Yoon Jung Min
• Do Hyungrok
• Koh Dae-Hyun

Classifications

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/065 Primary

  Differential amplifiers of latching type · CPC title

• H03F3/16

  with field-effect devices · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title