Data storage with multi-level read destructive memory

Patent metadata

Field	Value
Publication number	US-11868621-B2
Application number	US-202217844174-A
Country	US
Kind code	B2
Filing date	Jun 20, 2022
Priority date	Jun 22, 2021
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

A data storage system can employ a read destructive memory configured with multiple levels. A non-volatile memory unit can be programmed with a first logical state in response to a first write voltage of a first hysteresis loop by a write controller prior to being programmed to a second logical state in response to a second write voltage of the first hysteresis loop, as directed by the write controller. The first and second logical states may be present concurrently in the non-volatile memory unit and subsequently read concurrently as the first logical state and the second logical state.

First claim

What is claimed is:

1. A method comprising:
programming a non-volatile memory unit with a first logical state in response to a first write voltage of a first hysteresis loop, as directed by a write controller;
programming the non-volatile memory unit with a second logical state in response to a second write voltage of the first hysteresis loop, the first and second logical states present concurrently in the non-volatile memory unit;
reading the first and second logical states from the non-volatile memory unit concurrently; and
testing, with a monitor circuit, the non-volatile memory unit during satisfaction of a host generated data access request to the non-volatile memory unit with an alternate read voltage selected by the monitor circuit.

2. The method of claim 1 , wherein the non-volatile memory unit comprises a ferroelectric memory cell and an antiferroelectric memory cell.

3. The method of claim 2 , wherein the ferroelectric memory cell is connected to the antiferroelectric memory cell in series.

4. The method of claim 2 , wherein the ferroelectric memory cell is connected to the antiferroelectric memory cell in parallel.

5. The method of claim 1 , wherein the alternate read voltage is selected to concurrently read at least one logical state from the non-volatile memory unit while indicating if a wear condition is present in the non-volatile memory unit.

6. The method of claim 1 , wherein the alternate read voltage is different than a reference voltage used to previously read the first and second logical states from the non-volatile memory unit.

7. The method of claim 1 , wherein the alternate read voltage has a greater latency than a reference voltage used to previously read the first and second logical states from the non-volatile memory unit.

8. The method of claim 1 , wherein the non-volatile memory unit has a read destructive construction.

9. A method comprising:
programming a non-volatile memory unit with different first and second logical states, as directed by a write controller, the first logical state corresponding with a first hysteresis loop, the second logical state corresponding with a second hysteresis loop, the first and second logical states each concurrently present in the non-volatile memory unit;
monitoring, with a monitor circuit, a health of at least one non-volatile memory unit by evaluating logged activity for a first group of non-volatile memory units; and
predicting, with the monitor circuit, a wear condition is present in a non-volatile memory unit of the first group of non-volatile memory units.

10. The method of claim 9 , wherein the monitor circuit changes a monitoring resolution from the first group of non-volatile memory units to a second group of non-volatile memory units, the first group and second group being different.

11. The method of claim 10 , wherein the first group consists of a greater number of non-volatile memory units than the second group.

12. The method of claim 10 , wherein the first group consists of a lower number of non-volatile memory units than the second group.

13. The method of claim 9 , wherein the monitor circuit alters a type of activity logged to monitor the health of the at least one non-volatile memory unit.

14. The method of claim 9 , wherein the monitor circuit prescribes a test data access operation to confirm the presence of the predicted wear condition.

15. The method of claim 9 , wherein the monitor circuit verifies the presence of the predicted wear condition during subsequent satisfaction of one or more host generated data access requests.

16. A method comprising:
programming a non-volatile memory unit with different first and second logical states, as directed by a write controller, the first logical state corresponding with a first hysteresis loop, the second logical state corresponding with a second hysteresis loop, the first and second logical states each concurrently present in the non-volatile memory unit;
determining, with a wear circuit, a wear condition is present in the non-volatile memory unit; and
altering, with a manipulation circuit, at least one operational parameter of the non-volatile memory unit to mitigate operational degradation corresponding with the wear condition.

17. The method of claim 16 , wherein altering the at least one operational parameter returns the first hysteresis loop to a default configuration from a wear configuration corresponding with the wear condition.

18. The method of claim 16 , wherein altering the at least one operational parameter increases a margin between logical states in the first hysteresis loop.

19. The method of claim 16 , wherein altering the at least one operational parameter changes a configuration of the first hysteresis loop without changing a configuration of the second hysteresis loop.

20. The method of claim 16 , wherein altering of the at least one operational parameter proactively customizes operation of the second hysteresis loop to prevent a wear condition from occurring.

Assignees

• Seagate Technology Llc

Inventors

• Trantham Jon D
• Viraraghavan Praveen
• Dykes John W
• Gilbert Ian J
• Kalarickal Sangita Shreedharan
• Totin Matthew J
• El-Batal Mohamad
• Mehta Darshana H

Classifications

• G06F3/0616 Primary

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C29/08

  Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing · CPC title

• G11C29/4401 Primary

  for self repair · CPC title