Input buffer circuit

Patent metadata

Field	Value
Publication number	US-11863189-B2
Application number	US-202117338107-A
Country	US
Kind code	B2
Filing date	Jun 3, 2021
Priority date	Mar 5, 2021
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

An integrated circuit includes an upper threshold circuit, a lower threshold circuit, and a control circuit. The upper threshold circuit is configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage. The lower threshold circuit is configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage. The control circuit is configured to change an output voltage signal from a first voltage level to a second voltage level when the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively.

First claim

What is claimed is:

1. An integrated circuit comprising:
an upper threshold circuit electrically connected to a first power domain and configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage, wherein the upper threshold circuit includes a first tracker configured to receive the input voltage signal and an upper threshold detector configured to generate the first enabling signal in response to a first signal received from the first tracker;
a first switch electrically connected between an upper supply voltage and a buffer output node, wherein the first switch is configured to be controlled by the first enabling signal;
a lower threshold circuit electrically connected to a second power domain and configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage, wherein the lower threshold circuit includes a second tracker configured to receive the input voltage signal and a lower threshold detector configured to generate the second enabling signal in response to a second signal received from the second tracker;
a second switch electrically connected between the buffer output node and a lower supply voltage wherein the second switch is configured to be controlled by the second enabling signal; and
a control circuit configured to change an output voltage signal from a first voltage level to a second voltage level when the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively, the control circuit comprising a regenerative circuit having at least one switch, and wherein a connection state of the at least one switch between the buffer output node and one of the upper supply voltage or the lower supply voltage is configured to be controlled with a voltage on the buffer output node.

2. The integrated circuit of claim 1 , wherein:
the control circuit is configured to change the output voltage signal from the first voltage level to the second voltage level if the first enabling signal changes a logic level after the second enabling signal changes the logic level.

3. The integrated circuit of claim 1 , wherein:
the control circuit is configured to change the output voltage signal from the second voltage level to the first voltage level if the first enabling signal changes a logic level before the second enabling signal changes the logic level.

4. The integrated circuit of claim 1 , wherein:
the first voltage level is equal to the lower supply voltage; and
the second voltage level is equal to the upper supply voltage.

5. The integrated circuit of claim 1 , wherein:
the upper threshold circuit is configured to be powered by the upper supply voltage and an intermediate lower supply voltage.

6. The integrated circuit of claim 1 , wherein:
the lower threshold circuit is configured to be powered by an intermediate upper supply voltage and the lower supply voltage.

7. The integrated circuit of claim 1 , wherein the upper threshold circuit comprises:
a high-side tracker configured to receive the input voltage signal; and
an upper threshold detector configured to receive an tracking-up signal from the high-side tracker.

8. The integrated circuit of claim 1 , wherein the lower threshold circuit comprises:
a low-side tracker configured to receive the input voltage signal; and
a lower threshold detector configured to receive a tracking-down signal from the low-side tracker.

9. The integrated circuit of claim 1 , where each of the upper supply voltage and the lower supply voltage is coupled to the buffer output node through one switch in the regenerative circuit controlled by the voltage on the buffer output node.

10. The integrated circuit of claim 1 , further comprising:
a level shifter configured to receive the output voltage signal from the control circuit; and
wherein the level shifter is configured to generate a second output voltage signal in the second power domain based on the output voltage signal received.

11. A method comprising:
generating a first enabling signal based on comparing an input voltage signal with an upper threshold voltage, wherein generating the first enabling signal includes generating the first enabling signal with an upper threshold circuit in response to a first signal received from a first tracker coupled to the input voltage signal;
controlling a first switch with the first enabling signal, wherein the first switch is electrically connected between an upper supply voltage and a buffer output node;
generating a second enabling signal based on comparing the input voltage signal with a lower threshold voltage, wherein generating the second enabling signal includes generating the second enabling signal with a lower threshold circuit in response to a second signal received from a second tracker coupled to the input voltage signal;
controlling a second switch with the second enabling signal, wherein the second switch is electrically connected between the buffer output node and a lower supply voltage;
controlling at least one switch in a regenerative circuit with a voltage on the buffer output node to change a connection state of the at least one switch between the buffer output node and one of the upper supply voltage or the lower supply voltage; and
changing an output voltage signal from a first voltage level to a second voltage level when each of the first enabling signal and the second enabling signal changes a logical level consecutively.

12. The method of claim 11 , wherein changing the output voltage signal comprises:
changing the output voltage signal from the first voltage level to the second voltage level if the first enabling signal changes a logic level after the second enabling signal changes the logic level.

13. The method of claim 11 , wherein changing the output voltage signal comprises:
changing the output voltage signal from the second voltage level to the first voltage level if the first enabling signal changes a logic level before the second enabling signal changes the logic level.

14. An integrated circuit comprising:
an upper threshold circuit electrically connected to a first power domain and configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage, wherein the upper threshold circuit includes a first tracker configured to receive the input voltage signal and an upper threshold detector configured to generate the first enabling signal in response to a first signal received from the first tracker;
a lower threshold circuit electrically connected to a second power domain and configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage, wherein the lower threshold circuit includes a second tracker configured to receive the input voltage signal and a lower threshold detector configured to generate the second enabling signal in response to a second signal received from the second tracker;
a first switch electrically connected between an upper supply voltage and a buffer output node and configured to receive the first enabling signal from the upper threshold circuit;
a second switch electrically connected between the buffer output node and a lower supply voltage and configured to receive the second enabling signal from the lower threshold circuit; and
a regenerative circuit having at least one switch coupled between the buffer output node and one of the upper supply voltage or the lower supply voltage, and wherein a connectio

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Yu-Kai
• Chen Chia-Hui
• Chang Chia-Jung

Classifications

• H03K3/0377 Primary

  Bistables with hysteresis, e.g. Schmitt trigger (non-regenerative amplitude discriminators G01R19/165) · CPC title

• H03K3/13

  Bistables with hysteresis, e.g. Schmitt trigger · CPC title

• H03K3/3565

  Bistables with hysteresis, e.g. Schmitt trigger · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title