Pulsed level shift and inverter circuits for GaN devices

Patent metadata

Field	Value
Publication number	US-11862996-B2
Application number	US-202217811797-A
Country	US
Kind code	B2
Filing date	Jul 11, 2022
Priority date	Sep 16, 2014
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

First claim

What is claimed is:

1. A circuit comprising:
a first transistor having a first gate terminal, a first source terminal and a first drain terminal; and
a second transistor having a second gate terminal, a second source terminal and a second drain terminal;
wherein the first drain terminal is coupled to the second source terminal;
wherein the first transistor is a gallium nitride (GaN)-based lateral high electron mobility transistor (HEMT) and the second transistor is a GaN-based lateral HEMT;
wherein the first transistor is disposed on a first GaN-based substrate and the second transistor is disposed on a second GaN-based substrate; and wherein the first GaN-based substrate contains only the first transistor, and the second GaN-based substrate only contains the second transistor.

2. The circuit of claim 1 , wherein the first transistor is an enhancement-mode GaN-based transistor.

3. The circuit of claim 2 , wherein the second transistor is an enhancement-mode GaN-based transistor.

4. The circuit of claim 1 , further comprising a first gate driver circuit coupled to the first gate terminal, wherein the first gate driver circuit is disposed on a third substrate and arranged to receive a first input signal that is referenced to ground and control a conductivity state of the first transistor.

5. The circuit of claim 4 , further comprising a second gate driver circuit coupled to the second gate terminal, wherein the second gate driver circuit is disposed on the third substrate and arranged to receive a second input signal that is referenced to a floating voltage and control conductivity state of the second transistor.

6. An electronic component comprising:
a package base;
one or more semiconductor dies secured to the package base and comprising:
a first transistor having a first gate terminal, a first source terminal and a first drain terminal; and
a second transistor having a second gate terminal, a second source terminal and a second drain terminal;
wherein the first drain terminal is coupled to the second source terminal;
wherein the first transistor is a gallium nitride (GaN)-based lateral high electron mobility transistor (HEMT) and the second transistor is a GaN-based lateral HEMT;
wherein the one or more semiconductor dies comprise a first and second GaN-based dies and a third silicon-based die, and wherein the first transistor is disposed on the first GaN-based die, the second transistor is disposed on the second GaN-based die, and wherein the third silicon-based die comprises a first gate driver circuit coupled to the first gate terminal.

7. The electronic component of claim 6 , wherein the first transistor is an enhancement-mode GaN-based transistor.

8. The electronic component of claim 7 , wherein the second transistor is an enhancement-mode GaN-based transistor.

Assignees

• Navitas Semiconductor Ltd

Inventors

• Kinzer Daniel M
• Sharma Santosh
• Zhang Ju Jason

Classifications

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/481

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/411 Primary

  Chip-supporting parts, e.g. die pads · CPC title

• H10W42/80

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title