Sum address memory decoded dual-read select register file

Patent metadata

Field	Value
Publication number	US-11862289-B2
Application number	US-202117345299-A
Country	US
Kind code	B2
Filing date	Jun 11, 2021
Priority date	Jun 11, 2021
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

Aspects of the invention include decoding a base address and an offset to generate a first potential memory address and a second potential memory address. A first cell data associated with the first potential memory address of a first partitioned array and a second cell data associated with a second partitioned array are evaluated. Carry-out bit information is received from a summing operation of the base address and the offset, the operating being performed in parallel to the decoding. The carry-out bit information is used to select either the first cell data or the second cell data.

First claim

What is claimed is:

1. A computer-implemented method comprising:
decoding, by a processor, a base address and an offset to generate a first potential memory address and a second potential memory address;
evaluating, by the processor, a first cell data associated with the first potential memory address of a first partitioned array and a second cell data associated with a second partitioned array of a second partitioned array;
receiving, by the processor, carry-out bit information from a summing operation of the base address and the offset; and
selecting, by the processor, one of the first cell data and the second cell data based at least in part on the carry-out bit information.

2. The computer-implemented method of claim 1 , wherein the decoding is based at least in part on a most significant bit of the base address and a most significant bit of the offset.

3. The computer-implemented method of claim 1 , wherein the summing is based at least in part on an entirety of the base address and an entirety of the offset.

4. The computer-implemented method for claim 1 , wherein the summing operation of the base address and the offset is performed in parallel with the decoding.

5. The computer-implemented method of claim 1 , wherein the first potential memory address and the second potential memory address are sequential memory addresses.

6. The computer-implemented method of claim 1 , wherein the first partitioned array is an even entry array and the second partitioned array is an odd entry array.

7. The computer-implemented method of claim 1 , wherein a first bit of the first cell data is evaluated by a first single bitline evaluation circuit and a second bit of the second cell data is evaluation by a second single bitline evaluation circuit.

8. A system comprising:
a memory having computer readable instructions; and
one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
decoding a base address and an offset to generate a first potential memory address and a second potential memory address;
evaluating a first cell data associated with the first potential memory address of a first partitioned array and a second cell data associated with a second partitioned array of a second partitioned array;
receiving carry-out bit information from a summing operation of the base address and the offset; and
selecting one of the first cell data and the second cell data based at least in part on the carry-out bit information.

9. The system of claim 8 , wherein the decoding is based at least in part on a most significant bit of the base address and a most significant bit of the offset.

10. The system of claim 8 , wherein the summing is based at least in part on an entirety of the base address and an entirety of the offset.

11. The system of claim 8 , wherein the summing operation of the base address and the offset is performed in parallel with the decoding.

12. The system of claim 8 , wherein the first potential memory address and the second potential memory address are sequential memory addresses.

13. The system of claim 8 , wherein the first partitioned array is an even entry array and the second partitioned array is an odd entry array.

14. The system of claim 8 , wherein a first bit of the first cell data is evaluated by a first single bitline evaluation circuit and a second bit of the second cell data is evaluation by a second single bitline evaluation circuit.

15. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by one or more processors to cause the one or more processors to perform operations comprising:
decoding a base address and an offset to generate a first potential memory address and a second potential memory address;
evaluating a first cell data associated with the first potential memory address of a first partitioned array and a second cell data associated with a second partitioned array of a second partitioned array;
receiving carry-out bit information from a summing operation of the base address and the offset; and
selecting one of the first cell data and the second cell data based at least in part on the carry-out bit information.

16. The computer program product of claim 15 , wherein the decoding is based at least in part on a most significant bit of the base address and a most significant bit of the offset.

17. The computer program product of claim 15 , wherein the summing is based at least in part on an entirety of the base address and an entirety of the offset.

18. The computer program product of claim 15 , wherein the summing operation of the base address and the offset is performed in parallel with the decoding.

19. The computer program product of claim 15 , wherein the first potential memory address and the second potential memory address are sequential memory addresses.

20. The computer program product of claim 15 , wherein the first partitioned array is an even entry array and the second partitioned array is an odd entry array.

Assignees

• IBM

Inventors

• Wang Geoffrey
• Lee Michael
• Tran Kevin D

Classifications

• G11C7/1096 Primary

  Write circuits, e.g. I/O line write drivers · CPC title

• G06F7/505

  in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination · CPC title

• G06F7/74

  Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders {(with shifting G06F5/01)} · CPC title

• G11C7/103

  using serially addressed read-write data registers (G11C7/1036 takes precedence) · CPC title

• G11C7/1069

  I/O lines read out arrangements · CPC title