Sense amplifier, memory and control method of sense amplifier

Patent metadata

Field	Value
Publication number	US-11862285-B2
Application number	US-202117474166-A
Country	US
Kind code	B2
Filing date	Sep 14, 2021
Priority date	Sep 1, 2020
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

A sense amplifier, a memory and a method for controlling the sense amplifier are provided. The sense amplifier includes: an amplification module configured to read data in a storage unit on a first or second bit line; a control module electrically connected to the amplification module. When data in the storage unit on the first bit line is read, in a first amplification phase of the sense amplifier, the control module configures the amplification module to include a first current mirror structure and connects a mirror terminal of the first current mirror structure to the second bit line; when data in the storage unit on the second bit line is read, in the first amplification phase of the sense amplifier, the control module configures the amplification module to include a second current mirror structure and connects a mirror terminal of the second current mirror structure to the first bit line.

First claim

The invention claimed is:

1. A sense amplifier, comprising:
an amplification module, configured to read data in a storage unit on a first bit line or a second bit line; and
a control module, electrically connected to the amplification module;
wherein when the data in the storage unit on the first bit line is read, in a first amplification phase of the sense amplifier, the control module is configured to configure the amplification module to comprise a first current mirror structure and connect a mirror terminal of the first current mirror structure to the second bit line; and
when the data in the storage unit on the second bit line is read, in the first amplification phase of the sense amplifier, the control module is configured to configure the amplification module to comprise a second current mirror structure and connect a mirror terminal of the second current mirror structure to the first bit line;
wherein an operation phase of the sense amplifier comprises the first amplification phase and a second amplification phase, and a non-read bit line voltage is pre-amplified in a first direction during the first amplification phase, the first direction being opposite to a direction in which a read bit line voltage is amplified.

2. The sense amplifier of claim 1 , wherein the amplification module comprises:
a first positive channel metal oxide semiconductor (PMOS) transistor;
a second PMOS transistor;
a first negative channel metal oxide semiconductor (NMOS) transistor having a gate connected to the second bit line and a drain connected to a drain of the first PMOS transistor through a first node; and
a second NMOS transistor having a gate connected to the first bit line and a drain connected to a drain of the second PMOS transistor through a second node;
wherein when the data in the storage unit on the first bit line is read, in the first amplification phase of the sense amplifier, the control module is configured to configure the first PMOS transistor and the second PMOS transistor as the first current mirror structure and connect the second bit line to the second node; and
when the data in the storage unit on the second bit line is read, in the first amplification phase of the sense amplifier, the control module is configured to configure the first PMOS transistor and the second PMOS transistor as the second current mirror structure and connect the first bit line to the first node.

3. The sense amplifier of claim 2 , wherein the control module further comprises:
a first switch having a first terminal connected to a gate of the first PMOS transistor and a second terminal connected to a gate of the second PMOS transistor;
a second switch having a first terminal connected to the gate of the second PMOS transistor and a second terminal connected to the first node;
a third switch having a first terminal connected to the second node and a second terminal connected to the gate of the first PMOS transistor;
a fourth switch having a first terminal connected to the second node and a second terminal connected to the second bit line; and
a fifth switch having a first terminal connected to the first bit line and a second terminal connected to the first node;
wherein when the data in the storage unit on the first bit line is read, in the first amplification phase of the sense amplifier, the first switch, the second switch and the fourth switch are closed, and the third switch and the fifth switch are open; and
when the data in the storage unit on the second bit line is read, in the first amplification phase of the sense amplifier, the first switch, the third switch and the fifth switch are closed, and the second switch and the fourth switch are open.

4. The sense amplifier of claim 3 , wherein in the first amplification phase of the sense amplifier, sources of the first PMOS transistor and the second PMOS transistor receive a first voltage, and sources of the first NMOS transistor and the second NMOS transistor are connected to ground.

5. The sense amplifier of claim 4 , wherein when the data in the storage unit on the first bit line is read, in an offset compensation phase of the sense amplifier, the control module is configured to configure the amplification module to comprise the first current mirror structure and a first diode structure; and
when the data in the storage unit on the second bit line is read, in the offset compensation phase of the sense amplifier, the control module is configured to configure the amplification module to comprise the second current mirror structure and a second diode structure.

6. The sense amplifier of claim 5 , wherein the control module further comprises:
a sixth switch having a first terminal connected to the first node and a second terminal connected to the second bit line; and
a seventh switch having a first terminal connected to the first bit line and a second terminal connected to the second node;
wherein in the first amplification phase of the sense amplifier, the sixth switch and the seventh switch are open; when the data in the storage unit on the first bit line is read, in the offset compensation phase of the sense amplifier, the sixth switch is open and the seventh switch is closed; and when the data in the storage unit on the second bit line is read, in the offset compensation phase of the sense amplifier, the sixth switch is closed and the seventh switch is open.

7. The sense amplifier of claim 6 , wherein in the offset compensation phase of the sense amplifier, the sources of the first PMOS transistor and the second PMOS transistor receive the first voltage, and the sources of the first NMOS transistor and the second NMOS transistor are connected to ground.

8. The sense amplifier of claim 6 , wherein the control module is configured to configure the amplification module as a cross-coupled amplification structure in the second amplification phase after the first amplification phase of the sense amplifier.

9. The sense amplifier of claim 8 , wherein in the second amplification phase of the sense amplifier, the first switch, the sixth switch and the seventh switch are open, and the second switch, the third switch, the fourth switch and the fifth switch are closed.

10. The sense amplifier of claim 9 , wherein in the second amplification phase of the sense amplifier, the sources of the first PMOS transistor and the second PMOS transistor receive the first voltage, and the sources of the first NMOS transistor and the second NMOS transistor are connected to ground.

11. The sense amplifier of claim 10 , wherein there is an inductive phase of the sense amplifier between the offset compensation phase and the first amplification phase of the sense amplifier;
when the data in the storage unit on the first bit line is read, in the inductive phase of the sense amplifier, the first switch and the second switch are closed, and the third switch, the fourth switch, the fifth switch, the sixth switch and the seventh switch are open; and
when the data in the storage unit on the second bit line is read, in the inductive phase of the sense amplifier, the first switch and the third switch are closed, and the second switch, the fourth switch, the fifth switch, the sixth switch and the seventh switch are open.

12. The sense amplifier of claim 11 , further comprising:
a precharge module, configured to perform precharge on the first bit line and the second bit line in a precharge phase before the offset compensation phase of the sense amplifier.

13. The sense amplifier of claim 12 , wherein in the precharge phase of the sense amplifier, the sources of the first PMOS transistor, the second PMOS transistor, the first NMOS tra

Assignees

• Univ Anhui
• Changxin Memory Tech Inc

Inventors

• Lin Zhiting
• Li Jianqing
• He Jun
• Ying Zhan
• Li Xin
• Cao Kanyu
• Lu Wenjuan
• Peng Chunyu
• Wu Xiulong
• Chen Junning

Classifications

• G11C7/08 Primary

  Control thereof · CPC title

• G11C7/062

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C7/065

  Differential amplifiers of latching type · CPC title