Memory device

Patent metadata

Field	Value
Publication number	US-11862220-B2
Application number	US-202217836228-A
Country	US
Kind code	B2
Filing date	Jun 9, 2022
Priority date	Oct 13, 2021
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

Provided is a memory device. The memory device may include a substrate, a ferroelectric field effect transistor disposed on the substrate, a first channel contacting a gate structure of the ferroelectric field effect transistor and extending in a vertical direction from the gate structure of the ferroelectric field effect transistor, a selection word line disposed at one side of the first channel, a first gate dielectric layer disposed between the first channel and the selection word line, and a cell word line disposed on top of the first channel.

First claim

What is claimed is:

1. A memory device comprising:
a substrate;
a ferroelectric field effect transistor disposed on the substrate;
a first channel contacting a gate structure of the ferroelectric field effect transistor and extending in a vertical direction from the gate structure of the ferroelectric field effect transistor;
a selection word line disposed at a side of the first channel;
a first gate dielectric layer disposed between the first channel and the selection word line; and
a cell word line disposed on top of the first channel.

2. The memory device of claim 1 , wherein the gate structure comprises a ferroelectric layer and a gate layer stacked on the substrate.

3. The memory device of claim 2 , wherein the gate structure further comprises a second gate dielectric layer between the substrate and the ferroelectric layer.

4. The memory device of claim 1 , wherein a bottom portion of the gate structure is recessed into the substrate.

5. The memory device of claim 1 , wherein the ferroelectric field effect transistor comprises the gate structure disposed on the substrate, a first source/drain at one side of the gate structure, and a second source/drain at another side of the gate structure.

6. The memory device of claim 5 , further comprising a ground line that is in contact with the first source/drain.

7. The memory device of claim 6 , further comprising a bit line that is in contact with the second source/drain.

8. The memory device of claim 7 , wherein the ground line and the bit line extend in parallel to each other.

9. The memory device of claim 7 , wherein the ground line and the bit line extend not parallel to the selection word line.

10. The memory device of claim 7 , wherein the ground line and the bit line extend in parallel to the cell word line.

11. The memory device of claim 7 , further comprising an interlayer insulating layer disposed between the ground line and the selection word line and between the bit line and the selection word line.

12. The memory device of claim 11 , wherein the interlayer insulating layer further extends between the ground line and a top portion of the gate structure and between the bit line and the top portion of the gate structure.

13. The memory device of claim 1 , wherein the first gate dielectric layer contacts two opposite surfaces and a bottom surface of the selection word line.

14. The memory device of claim 1 , further comprising a second channel contacting the gate structure of the ferroelectric field effect transistor and extending in the vertical direction from the gate structure of the ferroelectric field effect transistor, and the selection word line passes between the first channel and the second channel.

15. The memory device of claim 14 , wherein the first gate dielectric layer further extends between the second channel and the selection word line.

16. The memory device of claim 15 , further comprising a channel connection layer disposed on and contacting the gate structure of the ferroelectric field effect transistor and connecting the first channel to the second channel.

17. The memory device of claim 16 , wherein the first gate dielectric layer further extends between the channel connection layer and the selection word line.

18. The memory device of claim 1 , further comprising a third gate dielectric layer disposed between the selection word line and the cell word line.

19. A memory device comprising:
a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell each comprising a ferroelectric field effect transistor and a field effect transistor, wherein the ferroelectric field effect transistor comprises a grounded first source/drain, a first gate structure, and a second source/drain, and the field effect transistor comprises a third source/drain connected to the first gate structure, a second gate structure, and a fourth source/drain;
a first selection word line connected to the second gate structure of each of the first memory cell and the second memory cell;
a second selection word line connected to the second gate structure of each of the third memory cell and the fourth memory cell;
a first bit line connected to the second source/drain of each of the first memory cell and the third memory cell;
a second bit line connected to the second source/drain of each of the second memory cell and the fourth memory cell;
a first cell word line connected to the fourth source/drain of each of the first memory cell and the third memory cell; and
a second cell word line connected to the fourth source/drain of each of the second memory cell and the fourth memory cell,
wherein, in a write operation on the fourth memory cell, a switching voltage is applied to the second selection word line, a write voltage is applied to the second cell word line, and 0 V is applied to the first bit line, the first selection word line, the first cell word line, and the second bit line.

20. A memory device comprising:
a substrate;
a gate structure comprising a first gate dielectric layer, a ferroelectric layer, and a gate layer stacked on the substrate;
a first source/drain disposed at one side of the gate structure;
a second source/drain disposed at another side of the gate structure;
a ground line in contact with the first source/drain and extending in a first horizontal direction;
a bit line in contact with the second source/drain and extending in the first horizontal direction;
a first channel and a second channel each contacting the gate structure, and each extending in a vertical direction from the gate structure;
a channel connection layer disposed on the gate layer, the channel connection layer connecting the first channel to the second channel, and contacting the gate structure;
a selection word line disposed between the first channel and the second channel and extending in a second horizontal direction;
a second gate dielectric layer extending between the first channel and the selection word line, between the second channel and the selection word line, and between the channel connection layer and the selection word line;
a cell word line disposed on top of the first channel and top of the second channel; and
a third gate dielectric layer disposed between the cell word line and the selection word line.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Minjun
• Kim Yongseok
• Kim Hyuncheol
• Park Jongman
• Woo Dongsoo
• Lee Kyunghwan

Classifications

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• G11C11/2273 Primary

  Reading or sensing circuits or methods · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C11/2255

  Bit-line or column circuits · CPC title

• G11C11/2257

  Word-line or row circuits · CPC title