Node with combined optical and electrical switching
US-2019335252-A1 · Oct 31, 2019 · US
US11860413B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11860413-B2 |
| Application number | US-202218070889-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 29, 2022 |
| Priority date | Mar 6, 2019 |
| Publication date | Jan 2, 2024 |
| Grant date | Jan 2, 2024 |
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Described herein are photonic communication platforms that can overcome the memory bottleneck problem, thereby enabling scaling of memory capacity and bandwidth well beyond what is possible with conventional computing systems. Some embodiments provide photonic communication platforms that involve use of photonic modules. Each photonic module includes programmable photonic circuits for placing the module in optical communication with other modules based on the needs of a particular application. The architecture developed by the inventors relies on the use of common photomask sets (or at least one common photomask) to fabricate multiple photonic modules in a single wafer. Photonic modules in multiple wafers can be linked together into a communication platform using optical or electronic means.
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The invention claimed is: 1. A photonic communication platform comprising: a semiconductor photonic substrate comprising an optical network having a plurality of optical waveguides and a plurality of optical transceivers coupled to respective optical waveguides, wherein the plurality of optical waveguides and the plurality of optical transceivers are lithographically patterned on the semiconductor photonic substrate; a plurality of processor chips mounted on the semiconductor photonic substrate and coupled to respective optical transceivers; and a networking chip mounted on the semiconductor photonic substrate and coupled to an optical transceiver of the plurality of optical transceivers; wherein: a first optical waveguide of the plurality of optical waveguides places a processor chip of the plurality of processor chips in communication with the networking chip, and the optical network places the processor chips in communication with each other in accordance with a multi-cast topology, whereby each processor chip is in direct communication with more than two other processor chips. 2. The photonic communication platform of claim 1 , wherein the processor chips are coupled to the respective optical transceivers via through-silicon vias, copper pillars, micro-bumps or ball-grid arrays. 3. The photonic communication platform of claim 1 , further comprising a memory chip, wherein a second optical waveguide of the plurality of optical waveguides places the processor chip of the plurality of processor chips in communication with the memory chip. 4. The photonic communication platform of claim 3 , wherein the photonic network is configured to: receive a first electrical signal from the processor chip; convert, using a first transceiver of the plurality of transceivers, the first electrical signal received from the processor chip to an optical signal; propagate the optical signal from the first transceiver to a second transceiver of the plurality of transceivers using the second optical waveguide; convert, using the second transceiver, the optical signal to a second electrical signal; and convey the second electrical signal to the memory chip. 5. The photonic communication platform of claim 1 , wherein the transceivers comprise optical modulators and optical receivers. 6. The photonic communication platform of claim 1 , wherein the photonic network is configured to: receive a first electrical signal from the processor chip; convert, using a first transceiver of the plurality of transceivers, the first electrical signal received from the processor chip to an optical signal; propagate the optical signal from the first transceiver to a second transceiver of the plurality of transceivers using the first optical waveguide; convert, using the second transceiver, the optical signal to a second electrical signal; and convey the second electrical signal to the networking chip. 7. The photonic communication platform of claim 1 , wherein the processor chips and the networking chip are bonded to the semiconductor photonic substrate. 8. The photonic communication platform of claim 1 , wherein the semiconductor photonic substrate is a silicon photonics photonic substrate.
using lasers · CPC title
Multiplexers; Demultiplexers · CPC title
Wavelength-division multiplex systems · CPC title
comprising photonic band-gap structures or photonic lattices · CPC title
Combinations of two or more optical elements · CPC title
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