Isolator

Patent metadata

Field	Value
Publication number	US-11855659-B2
Application number	US-202218072070-A
Country	US
Kind code	B2
Filing date	Nov 30, 2022
Priority date	Mar 24, 2021
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

An isolator of embodiments includes a ΔΣ analog-digital converter configured to convert an analog signal into a digital signal of one bit and transmit the digital signal of one bit as normal data, a time direction multiplexing circuit configured to perform time direction multiplexing of alternately performing conversion of the normal data into a digital differential signal and transmission of the digital differential signal, and transmission of a special signal different from the normal data, and an insulated transmission circuit configured to transmit the digital differential signal and the special signal transmitted from the time direction multiplexing circuit via an insulating layer.

First claim

What is claimed is:

1. An isolator comprising:
an analog-digital converter configured to convert an analog input signal into a digital signal and transmit the digital signal as normal data;
a time direction multiplexing circuit configured to perform time direction multiplexing of alternately performing conversion of the normal data from the analog-digital converter into a digital differential signal and transmission of the digital differential signal, and transmission of a special signal different from an output of the analog-digital converter; and
an insulated transmission circuit configured to transmit the digital differential signal and the special signal transmitted from the time direction multiplexing circuit via an insulating layer.

2. The isolator according to claim 1 ,
wherein there are m types of the special signal, where m is an integer equal to or greater than 2, and
the time direction multiplexing circuit alternately performs conversion of the normal data into the digital differential signal and transmission of the digital differential signal in one operation clock, and transmission of the m types of the special signal in m operation clocks.

3. The isolator according to claim 1 , further comprising:
an abnormality detection circuit configured to determine whether or not an amplitude of the analog input signal exceeds an excessive input threshold and generate a determination signal indicating a determination result,
wherein the time direction multiplexing circuit
receives the determination signal,
in a case where the determination signal indicates that the amplitude of the analog input signal does not exceed the excessive input threshold, converts the normal data from the analog-digital converter into a digital differential signal and transmits the digital differential signal to the insulated transmission circuit, and
in a case where the determination signal indicates that the amplitude of the analog input signal exceeds the excessive input threshold, transmits the digital differential signal and the special signal which are subjected to the time direction multiplexing to the insulated transmission circuit.

4. The isolator according to claim 3 , wherein
the analog-digital converter is configured to convert the analog input signal into a digital signal of one bit as the normal data,
the time direction multiplexing circuit comprises:
a 2-divider configured to receive the determination signal and multiply a frequency of an operation clock by ½ and output the operation clock in a case where the determination signal indicates that the amplitude of the analog input signal exceeds the excessive input threshold;
a first AND gate configured to receive the normal data from the analog-digital converter;
a first XOR gate connected to the first AND gate in parallel and configured to receive the normal data from the analog-digital converter;
a second XOR gate configured to receive an output of the first AND gate;
a 3-input AND gate configured to receive an output of the second XOR gate, an output of the 2-divider and the determination signal;
a second AND gate configured to receive an output of the first XOR gate and the determination signal;
a first latch configured to receive an output of the 3-input AND gate and the operation clock; and
a second latch configured to receive an output of the second AND gate and the operation clock,
wherein an output of the first latch is input to the second XOR gate, and
an output of the second latch is input to the first AND gate and the first XOR gate.

5. The isolator according to claim 4 ,
wherein the time direction multiplexing circuit further comprises:
a first selector to which the normal data from the analog-digital converter, the output of the second XOR gate and the determination signal are connected,
wherein the first selector selects and outputs the normal data from the analog-digital converter in a case where the determination signal indicates that the amplitude of the analog input signal does not exceed the excessive input threshold, and
selects and outputs the output of the second XOR gate in a case where the determination signal indicates that the amplitude of the analog input signal exceeds the excessive input threshold.

6. The isolator according to claim 5 ,
wherein the time direction multiplexing circuit further comprises:
a differential output amplifier configured to convert an output from the first selector into the digital differential signal; and
a second selector to which the digital differential signal from the differential output amplifier, the special signal, and the output of the 2-divider are connected,
wherein the 2-divider is always reset and outputs 0 in a case where the determination signal indicates that the amplitude of the analog input signal does not exceed the excessive input threshold, and
the second selector outputs the digital differential signal from the differential output amplifier in a case where the output of the 2-divider is 0, and
alternately outputs the digital differential signal from the differential output amplifier and the special signal in a case where the output of the 2-divider is an output in which a frequency of the operation clock is multiplied by ½.

7. The isolator according to claim 1 ,
wherein the time direction multiplexing circuit comprises:
a low-pass filter circuit configured to perform low-pass filter processing on the normal data from the analog-digital converter; and
a decimation circuit and a quantizer configured to decimate the normal data of a plurality of bits subjected to the low-pass filter processing by the decimation circuit before or after quantizing the normal data of the plurality of bits subjected to the low-pass filter processing into one bit by the quantizer.

8. The isolator according to claim 1 ,
wherein the time direction multiplexing circuit comprises:
a low-pass filter circuit configured to perform low-pass filter processing on the normal data from the analog-digital converter;
a decimation circuit configured to decimate the normal data of a plurality of bits subjected to the low-pass filter processing; and
a noise shaping circuit configured to perform noise shaping processing of quantizing the normal data of the plurality of bits decimated by the decimation circuit to one bit and adding a quantization error upon quantization to next normal data of a plurality of bits to make quantization noise unevenly distributed on a high frequency side.

9. The isolator according to claim 8 ,
wherein the noise shaping circuit comprises:
an adder to which the normal data of the plurality of bits decimated by the decimation circuit is input;
a quantizer configured to quantize an output of the adder;
a subtractor configured to subtract the output quantized by the quantizer from the output of the adder; and
a delay element configured to delay an output of the subtractor, and
an output of the delay element is input to the adder and added to the normal data of the plurality of bits by the adder.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Nishikawa Masaki
• Ootaka Shoji

Classifications

• H03M3/464 Primary

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/344

  by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing · CPC title

• H03M3/466

  Multiplexed conversion systems · CPC title

• H03M3/368 Primary

  of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators · CPC title

• H03M3/462 Primary

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title