Electrostatic discharge protection circuit

Patent metadata

Field	Value
Publication number	US-11855075-B2
Application number	US-202217846569-A
Country	US
Kind code	B2
Filing date	Jun 22, 2022
Priority date	Jan 6, 2022
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

An electrostatic discharge protection circuit includes a pull-down switch, a dummy pattern arranged parallel to the pull-down switch in a first direction, clamp switches arranged parallel to each other in the first direction between the dummy pattern and the pull-down switch, and a resistor configured to transfer a power supply voltage supplied through a power terminal to a gate pattern of the pull-down switch by being arranged parallel to the pull-down switch. Drains of the clamp switches are coupled in common to the power terminal, sources of the clamp switches are coupled in common to a ground terminal, and a first end of the pull-down switch and a second end of the resistor are coupled to each other through a first conductive line extending in the first direction, the pull-down switch, the resistor and the first conductive line are formed in a same layer.

First claim

What is claimed is:

1. An electrostatic discharge protection circuit, comprising:
a pull-down switch;
a dummy pattern arranged parallel to the pull-down switch in a first direction;
clamp switches arranged parallel to each other in the first direction between the dummy pattern and the pull-down switch; and
a resistor arranged parallel to the pull-down switch and configured to transfer a power supply voltage supplied through a power terminal to a first gate pattern of the pull-down switch,
wherein drains of the clamp switches are coupled in common to the power terminal,
wherein sources of the clamp switches are coupled in common to a ground terminal, and
wherein a first end of the pull-down switch and a second end of the resistor are coupled to each other through a first conductive line extending in the first direction, the pull-down switch, the resistor and the first conductive line are formed in a same layer.

2. The electrostatic discharge protection circuit according to claim 1 , wherein the first gate pattern:
extends in a second direction perpendicular to the first direction, and
includes the first end of the pull-down switch and a third end of the pull-down switch in a direction opposite to the first end.

3. The electrostatic discharge protection circuit according to claim 2 , wherein the pull-down switch includes:
a source contacting the first end of the pull-down switch; and
a drain contacting the third end of the pull-down switch.

4. The electrostatic discharge protection circuit according to claim 1 , wherein the clamp switches:
extend in a second direction perpendicular to the first direction, and
include second gate patterns arranged parallel to each other in the first direction.

5. The electrostatic discharge protection circuit according to claim 4 , wherein the drains and the sources of the clamp switches are alternately arranged parallel to each other in the first direction between the second gate patterns.

6. The electrostatic discharge protection circuit according to claim 4 , wherein fourth ends of the second gate patterns are coupled to a drain of the pull-down switch through contacts and a second conductive line.

7. The electrostatic discharge protection circuit according to claim 6 , wherein the contacts include:
first contacts formed over the fourth ends of the second gate patterns; and
a second contact formed over the drain of the pull-down switch.

8. The electrostatic discharge protection circuit according to claim 7 , wherein the second conductive line is disposed over the first contacts and the second contact.

9. The electrostatic discharge protection circuit according to claim 1 , wherein the dummy pattern, the clamp switches, the pull-down switch, the first conductive line, and the resistor are formed over a first well.

10. The electrostatic discharge protection circuit according to claim 9 , further comprising a first junction region in the first well, wherein:
a top surface of the first junction region is exposed at a top of the first well, and
the first junction region has a rectangular pattern enclosing the dummy pattern, the clamp switches, the pull-down switch, the first conductive line, and the resistor.

11. The electrostatic discharge protection circuit according to claim 10 , wherein the first junction region is electrically coupled to the ground terminal.

12. The electrostatic discharge protection circuit according to claim 10 , further comprising a second well, wherein:
the second well comprises an N-type impurity injected into a substrate, and
the second well encloses the first well.

13. The electrostatic discharge protection circuit according to claim 12 , wherein a depth of the second well is equal to a depth of the first well.

14. The electrostatic discharge protection circuit according to claim 12 , further comprising a second junction region in the second well, wherein:
a top surface of the second junction region is exposed at a top of the second well, and
the second junction region has a rectangular pattern enclosing the first well in a region spaced apart from the first well.

15. The electrostatic discharge protection circuit according to claim 14 , wherein the second junction region is electrically coupled to the power terminal.

16. The electrostatic discharge protection circuit according to claim 12 , further comprising a third well, wherein:
the third well comprises an N-type impurity injected into the substrate, and
the third well encloses the second well.

17. The electrostatic discharge protection circuit according to claim 16 , wherein a concentration of the N-type impurity included in the third well is lower than a concentration of the N-type impurity included in the second well.

18. The electrostatic discharge protection circuit according to claim 16 , wherein a depth of the third well is greater than a depth of the second well.

19. The electrostatic discharge protection circuit according to claim 9 , wherein the first well comprises a P-type impurity injected into a substrate.

20. The electrostatic discharge protection circuit according to claim 9 , wherein a source of a first clamp switch, which is adjacent to the pull-down switch, among the clamp switches, and the first well are formed between a gate pattern of the first clamp switch and a gate pattern of the pull-down switch.

Assignees

• Sk Hynix Inc

Inventors

• Kim Do Hee

Classifications

• H10D89/931

  characterised by the dispositions of the protective arrangements · CPC title

• H10D89/911

  using passive elements as protective elements · CPC title

• H10D89/811 Primary

  using FETs as protective elements · CPC title

• H10D89/815

  involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base region of said parasitic bipolar transistor · CPC title

• H10D89/813

  specially adapted to provide an electrical current path other than the field-effect induced current path · CPC title