Semicondutor package substrate with die cavity and redistribution layer

Patent metadata

Field	Value
Publication number	US-11854922-B2
Application number	US-202117353805-A
Country	US
Kind code	B2
Filing date	Jun 21, 2021
Priority date	Jun 21, 2021
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

A semiconductor package includes a semiconductor substrate forming a cavity and a redistribution layer on a first side of the semiconductor substrate, the redistribution layer forming die contacts within the cavity and a set of terminals for the semiconductor package opposite the semiconductor substrate. The redistribution layer electrically connects one or more of the die contacts to the set of terminals. The semiconductor package further includes a semiconductor die including die terminals within the cavity with the die terminals electrically coupled to the die contacts within the cavity.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a semiconductor substrate including a cavity;
a redistribution layer on a first side of the semiconductor substrate, the redistribution layer

forming die contacts within the cavity on a first side of the semiconductor substrate and a set of terminals of the semiconductor package on a second side of the semiconductor substrate,
wherein the redistribution layer electrically connects one or more of the die contacts to the set of terminals; and
a semiconductor die including die terminals within the cavity with the die terminals electrically coupled to the die contacts within the cavity.

2. The semiconductor package of claim 1 , further comprising a mold compound covering the semiconductor die within the cavity.

3. The semiconductor package of claim 2 , wherein the mold compound serves as a underfill between the semiconductor die and the redistribution layer.

4. The semiconductor package of claim 1 , wherein the semiconductor die is recessed within the cavity.

5. The semiconductor package of claim 1 , further comprising solder connections electrically coupling the die terminals to the die contacts within the cavity.

6. The semiconductor package of claim 1 ,
wherein the redistribution layer forms passive component contacts on the same side as the die contacts,
wherein the semiconductor substrate includes vias adjacent the passive component contacts,
the package further comprising a passive component with passive component terminals mounted to the semiconductor substrate opposite the redistribution layer,
wherein the passive component terminals are electrically connected to the passive component contacts by way of the vias.

7. The semiconductor package of claim 6 , wherein the vias includes solder connections between the passive component contacts of the redistribution layer and the passive component terminals of the passive component.

8. The semiconductor package of claim 6 , wherein the redistribution layer electrically connects the passive component contacts to one or more of the die contacts.

9. The semiconductor package of claim 6 , wherein the passive component includes one or more of a group consisting of:
a resistor;
an inductor; and
a capacitor.

10. The semiconductor package of claim 1 ,
wherein the semiconductor substrate is a silicon substrate, and
wherein the semiconductor die is a silicon die.

11. The semiconductor package of claim 1 , further comprising a die scale redistribution layer including:
a redistribution layer trace with capture pads in contact with the die terminals;
a dielectric layer over the redistribution layer trace; and
external contact pads in electrical contact with the redistribution layer trace through openings in the dielectric layer.

12. A method of forming a semiconductor package comprising:
forming a redistribution layer on a first side of a semiconductor substrate, the redistribution

layer including die contacts adjacent the first side of the semiconductor substrate and a set of terminals of the semiconductor package adjacent a second side of the semiconductor substrate;
forming a cavity in the semiconductor substrate adjacent to the die contacts;
placing a semiconductor die including die terminals within the cavity with the die terminals facing the redistribution layer; and
electrically coupling the die terminals to the die contacts.

13. The method of claim 12 , further comprising covering the semiconductor die within the cavity with a mold compound.

14. The method of claim 12 , wherein the semiconductor die is positioned fully within the cavity.

15. The method of claim 12 , wherein the electrically coupling the die terminals to the die contacts of the redistribution layer within the cavity includes reflowing solder bumps.

16. The method of claim 12 , wherein forming the cavity in the semiconductor substrate adjacent to the die contacts includes:
masking a second side of a semiconductor substrate opposite the first side of the semiconductor substrate; and
etching the semiconductor substrate to expose the die contacts.

17. The method of claim 12 , wherein the redistribution layer further includes passive component contacts on the same side as the die contacts, the method further comprising:
forming vias adjacent the passive component contacts;
mounting a passive component with passive component terminals to the semiconductor substrate opposite the redistribution layer; and
electrically coupling the passive component terminals to the passive component contacts of the redistribution layer within the cavity.

18. The method of claim 17 , wherein the passive component includes one or more of a group consisting of:
a resistor;
an inductor; and
a capacitor.

19. The method of claim 12 , wherein the semiconductor substrate is a silicon substrate, and wherein the semiconductor die is a silicon die.

20. The method of claim 12 , wherein the semiconductor die includes:
a die scale redistribution layer over the die terminals; and
a dielectric layer over the die scale redistribution layer,
wherein the dielectric layer includes die terminal openings through which the die terminals are exposed.

21. The method of claim 12 , wherein the placing the semiconductor die includes placing an assembly comprising the semiconductor die and a die scale redistribution layer, the die scale redistribution layer including:
a redistribution layer trace with capture pads in contact with the die terminals;
a dielectric layer over the redistribution layer trace; and
external contact pads in electrical contact with the redistribution layer trace through openings in the dielectric layer.

22. The method of claim 12 ,
wherein semiconductor substrate is a semiconductor substrate for a plurality of semiconductor packages including the semiconductor package,
wherein forming the redistribution layer includes forming the redistribution layer for the plurality of semiconductor packages;
method further comprising:
forming cavities for each of the plurality of semiconductor packages;
placing semiconductor dies within the cavities for each of the plurality of semiconductor packages; and
singulating the plurality of semiconductor packages from semiconductor substrate to form a plurality of singulated semiconductor packages.

23. A semiconductor package, comprising:
a glass substrate forming a cavity;
a redistribution layer on a first side of the glass substrate, the redistribution layer forming die contacts within the cavity and a set of terminals for the semiconductor package opposite the glass substrate,
wherein the redistribution layer electrically connects one or more of the die contacts to the set of terminals; and
a semiconductor die including die terminals within the cavity with the die terminals electrically coupled to the die contacts within the cavity.

24. The semiconductor package of claim 23 , wherein the glass substrate includes one or more of a group consisting of:
fused silica;
quartz;
single crystal quartz; borosilicate glass; soda lime glass;
barium borosilicate glass; crown glass;
boro-aluminosilicate glass; and
indium tin oxide glass.

Assignees

• Texas Instruments Inc

Inventors

• Sridharan Vivek Swaminathan
• Manack Christopher Daniel
• Liu Joseph

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W90/00

  Package configurations · CPC title