Systems, methods and devices for determining work placement on processor cores

Patent metadata

Field	Value
Publication number	US-11853809-B2
Application number	US-202217857394-A
Country	US
Kind code	B2
Filing date	Jul 5, 2022
Priority date	Jan 15, 2016
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.

First claim

What is claimed is:

1. An apparatus, comprising:
a processor including a plurality of cores and a core assignment module operable by the processor to:
identify a ranked list of a subset of cores of the plurality of cores that have different physical characteristics than remaining core(s) of the plurality of cores;
determine whether a first count of thread(s) selected for optimization is less than or equal to a second count of the cores of the ranked list;
in response to a determination that the first count is less than or equal to the second count:
perform a first affinitization of an initial thread of the selected thread(s) to a core of an initial entry in the ranked list; and
perform one or more second affinitizations of any one or more next threads, respectively, of the selected thread(s) to one or more cores of one or more next entries in the ranked list, respectively; and
in response to a determination that the first count is greater than the second count, unaffinitize at least one thread-core affinitization of at least one uncompleted thread that is different than the thread(s) selected for optimization, the at least one thread-core affinitization corresponding to the subset of core(s).

2. The apparatus of claim 1 , wherein the cores of the ranked list have first operating voltages, respectively, that are lower than one or more second operating voltages, respectively, of the remaining core(s).

3. The apparatus of claim 2 , wherein at least one core of the cores of the ranked list is associated with a same operating frequency as at least one of the remaining core(s).

4. The apparatus of claim 2 , wherein at least one core of the ranked list is associated with a different operating frequency than at least one core of the remaining core(s).

5. The apparatus of claim 1 , wherein at least one of the cores of the ranked list corresponds to a user-selection input via a user interface.

6. The apparatus of claim 1 , wherein at least one of the cores of the ranked list corresponds to data of a fuse table.

7. The apparatus of claim 1 , wherein unaffinitize at least one thread-core affinitization comprises unaffinitize all thread-core affinitizations corresponding to at least one core of the cores of the ranked list.

8. The apparatus of claim 7 , wherein the core assignment module is further to:
rank the thread(s) selected for optimization based on at least one of an inclusion list or user request received by a user interface.

9. The apparatus of claim 1 , wherein the core assignment module is further to, for each thread of the thread(s) selected for optimization, in response to a determination that a demand of the thread is greater than a threshold:
add the thread to a tracker list and sort the threads of the tracker list based on an inclusion list or a user request received via a user interface; and
select the sorted thread for affinitization.

10. The apparatus of claim 1 , wherein the threads selected for optimization are identified from a ranked list of threads.

11. A hardware memory having instructions stored thereon that, in response to execution by a processing device, cause the processing device to perform operations, to:
identify a ranked list of a subset of cores of a plurality of cores that have different physical characteristics than remaining core(s) of the plurality of cores;
determine whether a first count of thread(s) selected for optimization based on processor core assignment is less than or equal to a second count of the cores the ranked list; and
in response to a determination that the first count is less than or equal to the second count:
perform a first affinitization of an initial thread of the selected thread(s) to a core of an initial entry in the list;
perform one or more second affinitizations of any one or more next threads, respectively, of the selected thread(s) to one or more cores of one or more next entries in the ranked list, respectively; and
in response to a determination that the first count is greater than the second count:
unaffinitize at least one thread-core affinitization of second thread(s) that are different than the first thread(s), wherein the second thread(s) comprise at least one uncompleted thread, the at least one thread-core affinitization corresponding to the subset of core(s).

12. The hardware memory of claim 11 , wherein unaffinitize at least one thread-core affinitization comprises unaffinitize all thread-core affinitizations corresponding to at least one core of the cores of the ranked list.

13. The hardware memory of claim 12 , wherein operations are further operable to:
rank the selected thread(s) based on at least one of an inclusion list or user request received by a user interface.

14. The hardware memory of claim 11 , wherein the operations include:
for each thread of the thread(s) selected for optimization, in response to a determination that a demand of the thread is greater than a threshold:
add the thread to a tracker list and sort the threads of the tracker list based on an inclusion list or a user request received via a user interface; and
select the sorted thread for affinitization.

15. The hardware memory of claim 11 , wherein the cores of the ranked list have one or more first operating voltages, respectively, that are lower than one or more second operating voltages, respectively, of the remaining core(s).

16. The hardware memory of claim 15 , wherein the at least one core of the cores of the ranked list is associated with a same operating frequency as at least one core of the remaining core(s).

17. The hardware memory of claim 15 , wherein the at least one core of the cores of the ranked list is associated with a different operating frequency than at least one core of the remaining core(s).

18. The hardware memory of claim 11 , wherein at least one of the cores of the ranked list corresponds to a user-selection input via a user interface.

19. The hardware memory of claim 11 , wherein at least one of the cores of the ranked list corresponds to data of a fuse table.

20. The hardware memory of claim 11 , wherein the threads selected for optimization are identified from a ranked list of threads.

Assignees

• Intel Corp

Inventors

• Therien Guy M
• Powell Michael D
• Ramani Venkatesh
• Biswas Arijit
• Sotomayor Guy G

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/329

  by task scheduling · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• G06F9/5083 Primary

  Techniques for rebalancing the load in a distributed system · CPC title