Energy Efficient Multi-Cluster System and Its Operations

Patent metadata

Field	Value
Publication number	US-2016139964-A1
Application number	US-201514936686-A
Country	US
Kind code	A1
Filing date	Nov 10, 2015
Priority date	Nov 17, 2014
Publication date	May 19, 2016
Grant date	—

Abstract

A multi-cluster system having processor cores of different energy efficiency characteristics is configured to operate with high efficiency such that performance and power requirements can be satisfied. The system includes multiple processor cores in a hierarchy of groups. The hierarchy of groups includes: multiple level-1 groups, each level-1 group including one or more of processor cores having identical energy efficiency characteristics, and each level-1 group configured to be assigned tasks by a level-1 scheduler; one or more level-2 groups, each level-2 group including respective level-1 groups, the processor cores in different level-1 groups of the same level-2 group having different energy efficiency characteristics, and each level-2 group configured to be assigned tasks by a respective level-2 scheduler; and a level-3 group including the one or more level-2 groups and configured to be assigned tasks by a level-3 scheduler.

First claim

What is claimed is:

1 . A computing system comprising:
a plurality of processor cores in a hierarchy of groups, the hierarchy of groups comprising:
a plurality of level-1 groups, each of the level-1 groups including one or more of the processor cores having identical energy efficiency characteristics, and each of the level-1 groups configured to be assigned first tasks by a respective level-1 scheduler;
one or more level-2 groups, each of the one or more level-2 groups including a respective plurality of level-1 groups, the processor cores in different level-1 groups of a same level-2 group having different energy efficiency characteristics, and each of the one or more level-2 groups configured to be assigned second tasks by a respective level-2 scheduler; and
a level-3 group including the one or more level-2 groups and configured to be assigned third tasks by a level-3 scheduler.

2 . The computing system of claim 1 , wherein the level-3 group further comprises one or more level-1 groups not belonging to any level-2 group.

3 . The computing system of claim 1 , wherein any two processor cores of different level-1 groups in a same level-2 group have closer energy efficiency characteristic curves than any two processor core of different level-1 groups in different level-2 groups.

4 . The computing system of claim 1 , wherein in each of the level-2 groups, an energy efficiency characteristic curve of each level-1 group defines at least one predetermined frequency spot crossing or adjacent to at least one other level-1 group in a same level-2 group.

5 . The computing system of claim 1 , wherein in each of the level-2 groups, an energy efficiency characteristic curve of each level-1 group is at least a threshold distance away from an energy efficiency characteristic curve of each level-1 group in a different level-2 group.

6 . The computing system of claim 1 , wherein each of the level-1 groups has a Symmetric Multiprocessing (SMP) architecture.

7 . The computing system of claim 1 , wherein the respective level-1 scheduler is an SMP scheduler.

8 . The computing system of claim 1 , wherein the level-3 group has a Heterogeneous Multiprocessing (HMP) architecture.

9 . The computing system of claim 1 , wherein the level-3 scheduler is an HMP scheduler.

10 . The computing system of claim 1 , wherein the level-3 scheduler is an In-kernel switcher (IKS) scheduler.

11 . The computing system of claim 1 , wherein each of the level-2 groups has an Asymmetric Multiprocessing (AMP) architecture.

12 . The computing system of claim 1 , wherein the level-2 scheduler is an IKS scheduler.

13 . The computing system of claim 1 , wherein the level-2 scheduler is an AMP scheduler.

14 . The computing system of claim 13 , wherein in each of the level-2 groups, each level-1 group has one or more predetermined frequency spots, each frequency spot associated with the level-1 group and a respective other level-1 group in the same level-2 group.

15 . The computing system of claim 13 , wherein the AMP scheduler of one level-2 group is configured to detect an event in which a current operating frequency of an active level-1 group in the level-2 group enters or crosses any of one or more predetermined frequency spots of the active level-1 group, wherein the active level-1 group includes one or more first processor cores; and
when the event is detected, the AMP scheduler is configured to:
identify a target level-1 group in the same level-2 group, wherein each first processor core in the active level-1 group and each second processor core in the target level-1 group have different energy efficiency characteristics;
activate at least one second processor core in the target level-1 group;
determine whether to migrate one or more interrupt requests from the active level-1 group to the target level-1 group; and
determine whether to deactivate at least one first processor core of the active level-1 group based on a performance and power requirement.

16 . The computing system of claim 1 , wherein after each of the lever-1 schedulers performs load balance between the processor cores in the corresponding level-1 group, each of the one or more lever-2 schedulers performs load balance between the processor cores in the corresponding level-2 group, and then the level-3 scheduler performs load balance between the processor cores in the level-3 group.

17 . A computing system comprising:
a plurality of processor cores in a hierarchy of groups, the hierarchy of groups comprising
a plurality of level-1 groups, each of the level-1 groups including one or more of the processor cores and configured to have a Symmetric Multiprocessing (SMP) architecture;
one or more level-2 groups, each of the one or more level-2 groups including a respective plurality of level-1 groups, the processor cores in different level-1 groups of the same level-2 group having different energy efficiency characteristics; and
a level-3 group, including the one or more level-2 groups and configured to have a Heterogeneous Multiprocessing (HMP) architecture.

18 . The computing system of claim 17 , wherein the one or more level-2 groups are at one of a plurality of internal levels of the hierarchy, each internal level including respective one or more level-2 groups.

19 . The computing system of claim 17 , wherein each of the level-1 groups is configured to be assigned with tasks by a respective SMP scheduler.

20 . The computing system of claim 17 , wherein each of the one or more level-2 groups is configured to be assigned with tasks by a respective level-2 scheduler.

21 . The computing system of claim 17 , wherein the level-3 group is configured to be assigned with tasks by a level-3 scheduler.

22 . A computing system comprising:
a plurality of processor cores in a hierarchy of groups, the hierarchy of groups comprising:
one or more leaf-level groups, at least two of the processor cores in at least one leaf-level group having different energy efficiency characteristics in a same leaf-level group, and each of the one or more leaf-level groups configured to be assigned first tasks by a respective leaf-level scheduler; and
a root-level group, including the one or more leaf-level groups and configured to be assigned second tasks by a root-level scheduler.

23 . The computing system of claim 22 , wherein any two processor cores of a same leaf-level group have closer energy efficiency characteristic curves than any two processor core of different leaf-level groups.

24 . The computing system of claim 22 , wherein in the at least one leaf-level group, an energy efficiency characteristic curve of each processor core defines at least one predetermined frequency spot crossing or adjacent to at least one other processor core in a same leaf-level group.

25 . The computing system of claim 22 , wherein in each of the leaf-level groups, an energy efficiency characteristic curve of each processor core is at least a threshold distance away from an energy efficiency characteristic curve of each processor core in a different leaf-level group.

26 . The computing system of claim 22 , wherein the leaf-level group scheduler is an Asymmetric Multiprocessing (AMP) scheduler.

27 . The computing system of claim 22 , wherein the root-level group has a Heterogeneous Multiprocessing (HMP) architecture.

28 .

Assignees

• Mediatek Inc

Inventors

• Chen Jia-Ming
• Chou Hung-Lin
• Chang ya-ting
• Chiu Shih-Yen
• Hsu Chia-Hao
• Lin Yu-Ming
• Huang Wan-Ching
• Yang Jen-Chieh
• Hsiao Pi-Cheng

Classifications

• G06F9/4893

  taking into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F9/5094 Primary

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F1/329

  by task scheduling · CPC title

• G06F9/5083

  Techniques for rebalancing the load in a distributed system · CPC title