Anti-resonance structure for dampening die package resonance

Patent metadata

Field	Value
Publication number	US-11848656-B2
Application number	US-202117357277-A
Country	US
Kind code	B2
Filing date	Jun 24, 2021
Priority date	Jun 24, 2021
Publication date	Dec 19, 2023
Grant date	Dec 19, 2023

Abstract

A power delivery network, circuit, and method reduce die package resonance of an integrated circuit (IC) die. Decoupling capacitors interact with equivalent series inductances (ESLs) of power conductors within a package carrier substrate create the die package resonance characteristic. In one form an anti-resonance tuning circuit has a first branch including a first inductance coupled to one of an IC die positive power supply conductor and an IC die negative power supply conductor, and a second branch coupled directly to a selected one of a carrier substrate positive or negative conductive structures, the second branch comprising a second inductance inductively coupled to the first inductance.

First claim

What is claimed is:

1. A circuit for reducing die package resonance of an integrated circuit (IC) die, the circuit comprising:
an anti-resonance tuning circuit comprising a first branch including a first inductance coupled to one of an IC die positive power supply conductor and an IC die negative power supply conductor, and a second branch coupled directly to a selected one of a carrier substrate positive or negative conductive structures, the second branch comprising a second inductance inductively coupled to the first inductance.

2. The circuit of claim 1 , in which the first branch is conductively coupled to an IC die positive power supply conductor, and the second branch is connected to a selected substrate negative conductive structure.

3. The circuit of claim 1 , in which the first inductance and the second inductance are constructed as plated through-hole conductors in the carrier substrate.

4. The circuit of claim 1 , in which the first inductance and the second inductance are constructed with conductors in adjacent planar layers of the carrier substrate.

5. The circuit of claim 4 , in which the carrier substrate is a coreless carrier substrate.

6. The circuit of claim 1 , further comprising a tuning capacitor and a dampening resistance coupled to the second inductance, wherein the dampening resistance comprises an equivalent series resistance (ESR) of the tuning capacitor.

7. The circuit of claim 6 , in which the tuning capacitor comprises a ceramic chip capacitor mounted on the carrier substrate.

8. The circuit of claim 6 , further comprising one or more decoupling capacitors electrically connected between the IC die positive and negative power supply conductors, the one or more decoupling capacitors and equivalent series inductances (ESLs) of power conductors within a carrier substrate holding the IC die together exhibiting the die package resonance, wherein second branch has a resonant frequency matching that of the die package resonance, and the second inductance and dampening resistance are sized to reduce the die package resonance below a predetermined threshold.

9. An integrated circuit structure comprising:
an integrated circuit (IC) die including positive and negative power supply conductors;
a package including a carrier substrate carrying the IC die, and positive and negative external power supply contacts coupled to the IC die positive and negative power supply conductors through respective positive and negative conductive structures of the carrier substrate, one or more decoupling capacitors electrically connected between the positive and negative power supply conductors, the one or more decoupling capacitors exhibiting die package resonance; and
an anti-resonance tuning circuit comprising a first branch including a first inductance coupled to one of the IC die positive or negative power supply conductors and a second branch connected to a selected one of the carrier substrate positive or negative conductive structures, the second branch comprising a second inductance inductively coupled to the first inductance.

10. The integrated circuit structure of claim 9 , in which the first branch is conductively coupled to the IC die positive power supply conductor and the second branch is connected to a selected substrate negative conductive structure.

11. The integrated circuit structure of claim 9 , in which the first inductance and the second inductance are constructed as plated through-hole conductors in the carrier substrate.

12. The integrated circuit structure of claim 9 , in which the first inductance and the second inductance are constructed with conductors in adjacent planar layers of the carrier substrate.

13. The integrated circuit structure of claim 12 , in which the carrier substrate is a coreless carrier substrate.

14. The integrated circuit structure of claim 9 , further comprising a tuning capacitor and a dampening resistance coupled to the second inductance, wherein the second inductance and dampening resistance are sized to reduce the die package resonance below a predetermined threshold.

15. The integrated circuit structure of claim 14 , wherein the tuning capacitor and dampening resistance are connected in series across first and second terminals of the second inductance, and further comprising a second resistor connecting between the second terminal of the first inductance and the selected one of the carrier substrate positive or negative conductive structures.

16. The integrated circuit structure of claim 14 , in which the tuning capacitor comprises a ceramic chip capacitor mounted on the carrier substrate.

17. The integrated circuit structure of claim 14 , in which the dampening resistance consists essentially of an equivalent series resistance (ESR) of the tuning capacitor.

18. The integrated circuit structure of claim 9 , in which the second branch has a resonant frequency matching that of the die package resonance.

19. A method of mitigating die package resonance in a packaged integrated circuit (IC) power distribution system, the method comprising:
supplying power to digital circuitry on the packaged IC with positive and negative power supply conductors on the packaged IC supplied through positive and negative conductive structures in an IC package;
operating the digital circuitry;
mitigating power supply deviations to the digital circuitry with one or more decoupling capacitors; and
inductively coupling feedback current through an inductance-capacitance (LC) tank circuit connected to at least one of the IC package positive or negative conductive structures, the LC tank circuit comprising a first branch including a first inductance coupled to at least one of the IC package positive or negative conductive structures, and a second branch coupled directly to a selected one of a carrier substrate positive or negative conductive structures, the second branch comprising a second inductance inductively coupled to the first inductance.

20. The method of claim 19 , in which the LC tank circuit has an impedance function including a zero at a frequency of the die package resonance.

21. The method of claim 19 , in which feeding back current further comprises feeding the current though a dampening resistor.

22. The method of claim 19 , in which feeding back current further comprises feeding the current through a tuning capacitor in the IC package.

Assignees

• Ati Technologies Ulc

Inventors

• Guo Fei

Classifications

• H10W70/635

  Through-vias · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/692

  Ceramics or glasses · CPC title