Electronic device and method of manufacturing the same

US11848366B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11848366-B2
Application numberUS-202117468098-A
CountryUS
Kind codeB2
Filing dateSep 7, 2021
Priority dateDec 23, 2019
Publication dateDec 19, 2023
Grant dateDec 19, 2023

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Provided are an electronic device including a dielectric layer having an adjusted crystal orientation and a method of manufacturing the electronic device. The electronic device includes a seed layer provided on a substrate and a dielectric layer provided on the seed layer. The seed layer includes crystal grains having aligned crystal orientations. The dielectric layer includes crystal grains having crystal orientations aligned in the same direction as the crystal orientations of the seed layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A ferroelectric thin film structure comprising: a seed layer on a substrate, the seed layer including crystal grains having aligned crystal orientations; and a dielectric layer on the seed layer, the dielectric layer comprising a ferroelectric and including crystal grains having crystal orientations aligned in the same direction as the crystal orientations of the seed layer, wherein a material of the seed layer is selected such that the aligned crystal orientations of the seed layer are stable at an annealing temperature of the dielectric layer. 2. A ferroelectric thin film structure of claim 1 , wherein the seed layer comprises at least one of an oxide, a nitride, a chalcogenide, and a two-dimensional insulator material. 3. A ferroelectric thin film structure of claim 2 , wherein the oxide comprises at least one oxide of Y, Si, Al, Hf, Zr, La, Mo, W, Ru, and Nb. 4. A ferroelectric thin film structure of claim 3 , wherein the oxide further comprises a dopant. 5. A ferroelectric thin film structure of claim 1 , wherein the seed layer has a thickness of about 0.5 nm to about 3 nm. 6. A ferroelectric thin film structure of claim 1 , wherein the dielectric layer comprises at least one oxide of Hf, Si, Al, Zr, Y, La, Gd, and Sr. 7. A ferroelectric thin film structure of claim 6 , wherein the dielectric layer further comprises a dopant. 8. A ferroelectric thin film structure of claim 1 , wherein the dielectric layer has a thickness of about 0.5 nm to about 20 nm. 9. A ferroelectric thin film structure of claim 1 , wherein the crystal orientations of the crystal grains of the seed layer and of the dielectric layer have a <111> orientation. 10. A ferroelectric thin film structure of claim 1 , further comprising: an amorphous dielectric layer on the seed layer. 11. An electronic device comprising the ferroelectric thin film structure of claim 1 . 12. The electronic device of claim 11 , wherein the electronic device is a transistor or a capacitor. 13. An electronic device comprising: a substrate; a first dielectric layer over the substrate, the first dielectric layer including crystal grains having aligned crystal orientations; a second dielectric layer over the substrate, the second dielectric layer including crystal grains having crystal orientations aligned in the substantially same direction as the crystal orientations of the first dielectric layer; and an electrode over the second dielectric layer; wherein the first dielectric layer has a lattice parameter different from a lattice parameter of the second dielectric layer, and the first dielectric layer has a thickness of about 0.5 nm to about 3 nm and the second dielectric layer has a thickness of about 0.5 nm to about 20 nm, and wherein a material of the first dielectric layer is selected such that the aligned crystal orientations of the first dielectric layer are stable at an annealing temperature of the second dielectric layer. 14. The electronic device of claim 13 , wherein the first dielectric layer comprises at least one of an oxide, a nitride, a chalcogenide, or a two-dimensional insulator material. 15. The electronic device of claim 13 , wherein the second dielectric layer comprises a ferroelectric. 16. The electronic device of claim 15 , wherein the second dielectric layer comprises at least one oxide of Hf, Si, Al, Zr, Y, La, Gd, or Sr. 17. The electronic device of claim 16 , wherein the second dielectric layer further comprises a dopant. 18. The electronic device of claim 13 , wherein the crystal orientations of the crystal grains of the first dielectric layer and of the second dielectric layer have a <111> orientation. 19. The electronic device of claim 13 , further comprising: an amorphous dielectric layer on the first dielectric layer. 20. A ferroelectric thin film structure comprising: a seed layer on a substrate, the seed layer including crystal grains having aligned crystal orientations; an electrode; and a dielectric layer between the seed layer and the electrode, the dielectric layer comprising a ferroelectric and including crystal grains having crystal orientations aligned in the same direction as the crystal orientations of the seed layer, wherein the seed layer comprises at least one of a nitride, a chalcogenide, and a two-dimensional insulator material.

Assignees

Inventors

Classifications

  • to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer · CPC title

  • Formation of intermediate materials · CPC title

  • Making the insulator · CPC title

  • with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

  • the material containing hafnium, e.g. HfO2 · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11848366B2 cover?
Provided are an electronic device including a dielectric layer having an adjusted crystal orientation and a method of manufacturing the electronic device. The electronic device includes a seed layer provided on a substrate and a dielectric layer provided on the seed layer. The seed layer includes crystal grains having aligned crystal orientations. The dielectric layer includes crystal grains ha…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D30/701. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 19 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).