Apparatus and method for processing floating-point numbers

Patent metadata

Field	Value
Publication number	US-11847429-B2
Application number	US-202217588671-A
Country	US
Kind code	B2
Filing date	Jan 31, 2022
Priority date	Jul 19, 2019
Publication date	Dec 19, 2023
Grant date	Dec 19, 2023

Abstract

Adder circuits and associated methods for processing a set of at least three floating-point numbers to be added together include identifying, from among the at least three numbers, at least two numbers that have the same sign—that is, at least two numbers that are both positive or both negative. The identified at least two numbers are added together using one or more same-sign floating-point adders. A same-sign floating-point adder comprises circuitry configured to add together floating-point numbers having the same sign and does not include circuitry configured to add together numbers having different signs.

First claim

What is claimed is:

1. An adder circuit configured to process an input set comprising at least three floating-point numbers (A, B, C, . . . N) to be summed, the input set including one or more positive numbers and one or more negative numbers, the circuit comprising:
multiplexing logic configured to identify at least two numbers in the input set that have the same sign; and
one or more same-sign floating-point adders configured to add together the identified at least two numbers, to produce one or more partial summation results,
wherein the one or more same-sign floating-point adders are implemented in fixed function circuitry, and wherein the one or more same-sign floating-point adders do not include circuitry configured to add together numbers having different signs.

2. The adder circuit of claim 1 , further comprising:
a first output, configured to output the one or more partial summation results; and
a second output, configured to output each remaining number from the input set, other than the identified at least two numbers having the same sign.

3. The adder circuit of claim 1 , further comprising at least one mixed-sign floating-point adder implemented in fixed function circuitry configured to add together floating-point numbers having signs that are the same or different,
wherein a first input of said at least one mixed-sign floating-point adder is coupled to an output of the one or more same-sign floating-point adders,
and a second input of said at least one mixed-sign floating-point adder is configured to receive at least one number from the input set, other than the identified at least two numbers.

4. The adder circuit of claim 1 , further comprising at least one mixed-sign floating-point adder implemented in fixed function circuitry configured to add together floating-point numbers having signs that are the same or different,
wherein the at least one mixed-sign floating-point adder is configured to add together a plurality of numbers derived from the input set, thereby calculating the sum of the input set, wherein at least one of the plurality of numbers is a partial summation result produced by a same-sign floating-point adder.

5. The adder circuit of claim 1 , wherein the one or more same-sign floating-point adders comprises a first array of same-sign floating-point adders and a second array of same-sign floating-point adders,
wherein the multiplexing logic is configured to:
evaluate at least a sign bit of each floating-point number of the input set;
pass each floating-point number of the input set to a respective input of the first array only if the sign bit of that floating-point number is zero; and
pass each floating-point number of the input set to a respective input of the second array only if the sign bit of that floating-point number is one;

the adder circuit further comprising a floating-point subtractor or mixed-sign floating-point adder, configured to combine an output of the second array with an output of the first array.

6. The adder circuit of claim 5 , wherein each of the first array and the second array comprises a logarithmic tree of same-sign floating-point adders.

7. The adder circuit of claim 5 , wherein the first array and the second array are two different physical arrays in hardware.

8. The adder circuit of claim 5 , wherein the first array and the second array are provided by a single physical array in hardware,
wherein the multiplexing logic is configured to:
pass floating-point numbers whose sign bit is zero to the single array in a first time interval; and
pass floating-point numbers whose sign bit is one to the single array in a second, different time interval.

9. The adder circuit of claim 1 , wherein the multiplexing logic is configured to sort the input set into positive numbers and negative numbers.

10. The adder circuit of claim 9 , wherein the one or more same-sign floating-point adders comprises an array of same-sign floating-point adders, the array having a plurality of inputs;
wherein the multiplexing logic comprises a rotating multiplexer configured to align a boundary between the positive numbers and negative numbers with a boundary between two same-sign floating-point adders in the array, such that each same-sign floating-point adder in the array receives inputs that have the same sign.

11. An integrated circuit manufacturing system comprising:
a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an adder circuit as claimed in claim 1 ;
a layout processing system configured to process the computer readable dataset description so as to generate a circuit layout description of an integrated circuit embodying the adder circuit; and
an integrated circuit generation system configured to manufacture the adder circuit according to the circuit layout description.

12. A method of manufacturing an adder circuit configured to process an input set comprising at least three floating-point numbers (A, B, C, . . . N) to be summed, the input set including one or more positive numbers and one or more negative numbers, the circuit comprising:
multiplexing logic configured to identify at least two numbers in the input set that have the same sign; and
one or more same-sign floating-point adders configured to add together the identified at least two numbers, to produce one or more partial summation results,
wherein the one or more same-sign floating-point adders are implemented in fixed function circuitry, and wherein the one or more same-sign floating-point adders do not include circuitry configured to add together numbers having different signs,
said method comprising inputting a computer readable dataset description of said adder circuit into the integrated circuit manufacturing system as set forth in claim 11 .

13. A machine-implemented method of processing an input set comprising at least three floating-point numbers (A, B, C, . . . N) to be summed, the input set including one or more positive numbers and one or more negative numbers, the method comprising:
identifying at least two numbers in the input set that have the same sign; and
adding together the identified at least two numbers using one or more same-sign floating-point adders, to produce one or more partial summation results;
wherein the one or more same-sign floating-point adders are implemented in fixed function circuitry, and wherein the one or more same-sign floating-point adders do not include circuitry configured to add together numbers having different signs.

14. The method of claim 13 , further comprising:
adding together the one or more partial summation results and each remaining number from the input set, thereby calculating the sum of the input set,
wherein said adding together comprises using at least one mixed-sign floating-point adder implemented in fixed function circuitry configured to add together floating-point numbers having signs that are the same or different.

15. The method of claim 13 , further comprising:
using a mixed-sign floating-point adder to add together a plurality of numbers derived from the input set, wherein at least one of the plurality of numbers is a partial summation result produced by a same-sign floating-point adder, thereby calculating the sum of the input set;
wherein the mixed-sign floating-point adder is implemented in fixed function circuitry configured to add together floating-point numbers having signs that are the same or different.

16. The method of claim 13 , wherein the one or more same-sign floating-point adders comprises a first array of same-s

Assignees

• Imagination Tech Ltd

Inventors

• Elliott Sam
• Kallen Jonas Olof Gunnar
• Van Benthem Casper

Classifications

• G06F7/485 Primary

  Adding; Subtracting {(G06F7/4833, G06F7/4836 take precedence)} · CPC title

• G06F7/24

  Sorting, i.e. extracting data from one or more carriers, rearranging the data in numerical or other ordered sequence, and rerecording the sorted data on the original carrier or on a different carrier or set of carriers {sorting methods in general}(G06F7/36 takes precedence) · CPC title

• G06F7/501

  Half or full adders, i.e. basic adder cells for one denomination · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G06F7/575 Primary

  Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry · CPC title