Processor chip and control methods thereof

Patent metadata

Field	Value
Publication number	US-11842265-B2
Application number	US-202016906130-A
Country	US
Kind code	B2
Filing date	Jun 19, 2020
Priority date	Aug 13, 2019
Publication date	Dec 12, 2023
Grant date	Dec 12, 2023

Abstract

Disclosed in a processor chip configured to perform neural network processing. The processor chip includes a memory, a first processor configured to perform neural network processing on a data stored in the memory, a second processor and a third processor, and the second processor is configured to transmit a control signal to the first processor and the third processor to cause the first processor and the third processor to perform an operation.

First claim

What is claimed is:

1. A processor chip configured to perform neural network processing, comprising:
a neural processing unit (NPU), comprising a processor, configured to perform the neural network processing on data;
a central processing unit (CPU) comprising a processor;
a third processor; and
a memory configured to include a secure area that is accessible by the neural processing unit and is not accessible by the central processing unit, and an unsecure area accessible by the neural processing unit and the central processing unit,
wherein the central processing unit is configured to control to transmit a start signal to the third processor to cause the third processor to provide address information of one of a plurality of artificial intelligence models stored in the unsecure area included in the memory,
wherein the third processor is configured to:
identify the one of the plurality of artificial intelligence models based on a resolution of an input content,
provide the address information of the one of the plurality of artificial intelligence models to the neural processing unit so that the neural processing unit can perform the neural network processing by accessing the secure area based on the address information.

2. The processor chip according to claim 1 , wherein, the central processing unit is configured to:
transmit an initializing signal to the neural processing unit to cause the neural processing unit to perform the neural network processing on the input content based on address information of the input content provided by the third processor and artificial intelligence model information.

3. The processor chip according to claim 2 , wherein the neural processing unit is configured to obtain the artificial intelligence model information based on the address information of the artificial intelligence model provided by the third processor.

4. The processor chip according to claim 2 , further comprising:
a communication interface comprising communication circuitry;
wherein the processor chip is configured to store a plurality of frames included in the input content and sequentially received through the communication interface in the secure area of the memory, and
wherein the central processing unit is configured to transmit the start signal to the third processor to cause the third processor to provide address information of the frames sequentially stored in the memory to the neural processing unit at predetermined time intervals.

5. The processor chip according to claim 2 , wherein the central processing unit is configured to:
access the unsecure area included in the memory to identify address information of data corresponding to a second application based on the second application being executed,
provide the identified address information to the neural processing unit, and
control the neural processing unit to perform the neural network processing for the data based on address information of the data provided by the central processing unit and the artificial intelligence model information stored in the unsecure area.

6. The processor chip according to claim 1 , wherein the central processing unit is configured to transmit the start signal to the third processor to cause the third processor to provide information on the input content to the neural processing unit, based on a first application being executed.

7. The processor chip according to claim 6 , wherein the central processing unit is configured to transmit an end signal to the third processor to cause the third processor to stop providing information to the neural processing unit based on the first application being terminated, and
wherein the third processor is configured to control the neural processing unit to stop the neural network processing, and to provide a signal indicating that the neural network processing is stopped to the central processing unit.

8. The processor chip according to claim 1 ,
wherein the third processor includes a processor performing a predetermined operation.

9. The processor chip according to claim 1 , wherein the third processor is configured to identify address information of the input content by accessing the secure area and provide address information of the input content in the secure area to the neural processing unit at predetermined time intervals determined based on the input content.

10. A method of controlling a processor chip comprising a neural processing unit (NPU), a central processing unit (CPU), a third processor, and a memory including a secure area that is accessible by the neural processing unit and is not accessible by the central processing unit and an unsecure area accessible by the neural processing unit and the central processing unit, the method comprising:
transmitting, by the central processing unit, a start signal to the third processor to cause the third processor to provide address information of one of a plurality of artificial intelligence models stored in the unsecure area included in the memory;
based on receiving the start signal, the third processor identifying the one of the plurality of artificial intelligence models based on a resolution of an input content; and
providing, by the third processor, the address information of the one of a plurality of artificial intelligence models to the neural processing unit so that the neural processing unit performs neural network processing by accessing the secure area based on the address information.

11. The method according to claim 10 , wherein the method further comprises:
transmitting, by the central processing unit, an initializing signal to the neural processing unit to perform the neural network processing on the input content based on address information of the input content provided from the third processor and artificial intelligence model information.

12. The method according to claim 11 , wherein the method further comprises:
obtaining, by the neural processing unit, the artificial intelligence model information based on the address information of the artificial intelligence model provided by the third processor.

13. The method according to claim 11 , the method further comprising:
sequentially receiving a plurality of frames included in the input content and stored in the secure area of the memory; and
wherein the transmitting the start signal to the third processor comprises transmitting the start signal to the third processor to cause the third processor to provide the address information of frames sequentially stored in the memory to the neural processing unit at a predetermined time interval.

14. The method according to claim 11 , wherein the transmitting the start signal to the third processor comprises transmitting the start signal to the third processor to cause the third processor to provide information on the input content to the neural processing unit based on a first application being executed.

15. The method according to claim 14 , the method further comprising:
transmitting, by the central processing unit, an end signal to the third processor to cause the third processor to stop provided operations based on the first application being terminated;
terminating the neural network processing by the neural processing unit under control of the third processor; and
providing, by the third processor, a signal indicating that the neural network processing is terminated to the central processing unit.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Tai Yongmin
• Cho Insang
• Lee Wonjae
• Hwang Chanyoung

Classifications

• G06N3/063 Primary

  using electronic means · CPC title

• G06F12/1458

  by checking the subject access rights · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F21/79 Primary

  in semiconductor storage media, e.g. directly-addressable memories · CPC title

• G06F21/74

  operating in dual or compartmented mode, i.e. at least one secure mode · CPC title