Systems and methods of executing multiple hypervisors using multiple sets of processors

Patent metadata

Field	Value
Publication number	US-9606818-B2
Application number	US-201313829023-A
Country	US
Kind code	B2
Filing date	Mar 14, 2013
Priority date	Mar 14, 2013
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

An apparatus includes a primary hypervisor that is executable on a first set of processors and a secondary hypervisor that is executable on a second set of processors. The primary hypervisor may define settings of a resource and the secondary hypervisor may use the resource based on the settings defined by the primary hypervisor. For example, the primary hypervisor may program memory address translation mappings for the secondary hypervisor. The primary hypervisor and the secondary hypervisor may include their own schedulers.

First claim

What is claimed is:

1. An apparatus comprising:
a first set of hardware processors of a first instruction set architecture to execute a primary hypervisor, the primary hypervisor to schedule first virtual processor tasks for execution on the first set of hardware processors;
a second set of hardware processors of a second instruction set architecture to execute a secondary hypervisor, the secondary hypervisor to schedule second virtual processor tasks for execution on the second set of hardware processors, wherein the second instruction set architecture is different from the first instruction set architecture; and
a storage device to store memory address translation mapping data that is accessible to the primary hypervisor and to the secondary hypervisor, wherein the primary hypervisor is configured to program the memory address translation mapping data, and wherein the secondary hypervisor is configured to use the memory address translation mapping data.

2. The apparatus of claim 1 , wherein the first set of hardware processors includes only a single hardware processor, the second set of hardware processors includes only a single hardware processor, or any combination thereof.

3. The apparatus of claim 1 , wherein the first set of hardware processors includes multiple hardware processors, wherein the second set of hardware processors includes multiple hardware processors, or any combination thereof.

4. The apparatus of claim 1 , wherein the primary hypervisor has read-write access to the memory address translation mapping data and the secondary hypervisor has read-only access to the memory address translation mapping data.

5. The apparatus of claim 1 , wherein the secondary hypervisor is configured to access the memory address translation mapping data to perform processor virtualization.

6. The apparatus of claim 1 , wherein the primary hypervisor schedules the first virtual processor tasks in accordance with a first scheduling algorithm, and wherein the secondary hypervisor schedules the second virtual processor tasks in accordance with a second scheduling algorithm that is different from the first scheduling algorithm.

7. The apparatus of claim 6 , wherein at least one of the first scheduling algorithm and the second scheduling algorithm comprises time slice scheduling.

8. The apparatus of claim 6 , wherein at least one of the first scheduling algorithm and the second scheduling algorithm comprises priority-based scheduling.

9. The apparatus of claim 1 , further comprising:
a first guest operating system that is executable with respect to the first set of hardware processors; and
a second guest operating system that is executable with respect to the second set of hardware processors.

10. The apparatus of claim 1 , further comprising a guest operating system configured to concurrently execute on at least one processor of the first set of hardware processors and on at least one processor of the second set of hardware processors.

11. The apparatus of claim 1 , further comprising a virtualized device associated with the primary hypervisor, the secondary hypervisor, or a combination thereof.

12. The apparatus of claim 11 , wherein the virtualized device comprises a timer, and wherein the first set of hardware processors is distinct from the second set of hardware processors.

13. The apparatus of claim 1 , further comprising:
a first guest operating system that is executable by at least one of the first set of hardware processors, the first guest operating system configured to program second memory address translation mapping data to the storage device; and
a second guest operating system that is executable by at least one of the second set of hardware processors, the second guest operating system configured to program third memory address translation mapping data to the storage device.

14. An apparatus comprising:
a first set of hardware processors of a first instruction set architecture to execute a primary hypervisor, the primary hypervisor to schedule first virtual processor tasks for execution on the first set of hardware processors and comprising a first task scheduler associated with a first scheduling algorithm;
a second set of hardware processors of a second instruction set architecture to execute a secondary hypervisor, the secondary hypervisor to schedule second virtual processor tasks for execution on the second set of hardware processors and comprising a second task scheduler associated with a second scheduling algorithm that is distinct from the first scheduling algorithm, wherein the second instruction set architecture is different from the first instruction set architecture; and
a storage device to store memory address translation mapping data that is accessible to the primary hypervisor and to the secondary hypervisor, wherein the primary hypervisor is configured to program the memory address translation mapping data, and wherein the secondary hypervisor is configured to use the memory address translation mapping data.

15. The apparatus of claim 14 , wherein the primary hypervisor is configured to program memory address translation mapping data to a storage device, and wherein the secondary hypervisor is configured to use the memory address translation mapping data programmed by the primary hypervisor.

16. The apparatus of claim 15 , wherein the memory address translation mapping data indicates a translation from an intermediate physical address to a physical address.

17. An apparatus comprising:
a first set of hardware processors of a first instruction set architecture to execute a primary hypervisor, the primary hypervisor to schedule first virtual processor tasks for execution on the first set of hardware processors;
a second set of hardware processors of a second instruction set architecture to execute a secondary hypervisor, the secondary hypervisor to schedule second virtual processor tasks for execution on the second set of hardware processors, wherein the second instruction set architecture is different from the first instruction set architecture; and
a storage device to store memory address translation settings data of a resource that is accessible to the primary hypervisor and to the secondary hypervisor, wherein the primary hypervisor is configured to program the memory address translation settings data stored at the storage device, and wherein the secondary hypervisor is configured to use the resource based on the memory address translation settings data.

18. The apparatus of claim 17 , wherein the resource comprises at least a portion of a memory, a memory-mapped device, or any combination thereof.

19. The apparatus of claim 18 , wherein the memory address translation settings data comprises memory address translation mapping data.

20. The apparatus of claim 17 , wherein the primary hypervisor includes a first task scheduler associated with a first scheduling algorithm, and wherein the secondary hypervisor includes a second task scheduler associated with a second scheduling algorithm that is distinct from the first scheduling algorithm.

21. A method comprising:
determining, by a secondary hypervisor executing on a second set of hardware processors of a second instruction set architecture, one or more address translations from memory address translation mapping data programmed by a primary hypervisor executing on a first set of hardware processors of a first instruction set architecture, the primary hypervisor to schedule first virtual processor tasks for execution on

Assignees

• Qualcomm Inc

Inventors

• Plondke Erich James
• Codrescu Lucian
• Koob Christopher Edward
• Patel Piyush
• Sartorius Thomas Andrew

Classifications

• G06F9/45533 Primary

  Hypervisors; Virtual machine monitors · CPC title

• G06F12/109

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

• G06F2212/1021

  Hit rate improvement · CPC title

• G06F2212/151

  Emulated environment, e.g. virtual machine · CPC title

• G06F9/5016

  the resource being the memory · CPC title