Band-pass analog-to-digital converter using bidirectional voltage-controlled oscillator

Patent metadata

Field	Value
Publication number	US-11838028-B2
Application number	US-202217687110-A
Country	US
Kind code	B2
Filing date	Mar 4, 2022
Priority date	May 20, 2021
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

The present disclosure discloses a band-pass analog-to-digital converter (ADC) using a bidirectional voltage-controlled oscillator (VCO) including a first converter configured to receive an analog input signal and quantize the analog input signal according to a first clock signal to output a first digital signal, a second converter configured to receive the analog input signal and quantize the analog input signal in a time-interleaving manner according to a second clock signal, which has a phase opposite to that of the first clock signal, to output a second digital signal, and a multiplexer configured to receive the first and second digital signals and select one of the two signals in response to the first clock signal to finally output a digital output signal.

First claim

What is claimed is:

1. A band-pass analog-to-digital converter (ADC) using a bidirectional voltage-controlled oscillator (VCO), the ADC comprising:
a first converter configured to receive an analog input signal and quantize the analog input signal according to a first clock signal to output a first digital signal;
a second converter configured to receive the analog input signal and quantize the analog input signal in a time-interleaving manner according to a second clock signal, which has a phase opposite to that of the first clock signal, to output a second digital signal; and
a multiplexer configured to receive the first and second digital signals and select one of the two signals in response to the first clock signal to finally output a digital output signal,
wherein the first converter comprising:
a first sampling/holding part configured to sample a voltage level of the analog input signal at a rising edge of the first clock signal and hold the voltage level of the analog input signal until a next rising edge of the first clock signal to output a first sampling signal;
a first VCO configured to output a first oscillation signal having a frequency proportional to a voltage level of the first sampling signal in response to a third clock signal and a fourth clock signal each having a frequency of half of a frequency of the first clock signal; and
a first counter configured to count the number of pulse signals in the first oscillation signal to output the first digital signal.

2. The ADC of claim 1 , wherein the first VCO comprising:
a first time delayer configured to delay a time of the first sampling signal by operating a plurality of inverters connected in a forward direction or a plurality of inverters connected in a reverse direction according to a clock signal applied by receiving the first sampling signal; and
a first oscillation frequency controller connected to the first time delayer and configured to control a frequency of the first oscillation signal using a frequency of the first sampling signal to output a voltage swing.

3. The ADC of claim 2 , wherein the first time delayer comprising:
a first delayer configured to delay the time of the first sampling signal by supplying a power supply voltage to the plurality of inverters, which are built-in and connected in the forward direction, and simultaneously operating the plurality of inverters when the third clock signal is applied; and
a second delayer configured to delay the time of the first sampling signal by supplying the power supply voltage to the plurality of inverters, which are built-in and connected in the reverse direction, and simultaneously operating the plurality of inverters when the fourth clock signal having a phase opposite to that of the third clock signal is applied.

4. The ADC of claim 3 , wherein at a time point at which the applied clock signal is changed from the third clock signal to the fourth clock signal:
a voltage of the first oscillation signal at a corresponding node is held; and
a phase of the first oscillation signal is changed and proceeds in a direction opposite to a direction in which the phase initially proceeds.

5. The ADC of claim 1 , wherein the first counter counts rising edges of the pulse signals in the first oscillation signal.

6. A band-pass analog-to-digital converter (ADC) using a bidirectional voltage-controlled oscillator (VCO), the ADC comprising:
a first converter configured to receive an analog input signal and quantize the analog input signal according to a first clock signal to output a first digital signal;
a second converter configured to receive the analog input signal and quantize the analog input signal in a time-interleaving manner according to a second clock signal, which has a phase opposite to that of the first clock signal, to output a second digital signal; and
a multiplexer configured to receive the first and second digital signals and select one of the two signals in response to the first clock signal to finally output a digital output signal,
wherein the second converter comprising:
a second sampling/holding part configured to sample a voltage level of the analog input signal at a rising edge of the second clock signal and hold the voltage level of the analog input signal until a next rising edge of the second clock signal to output a second sampling signal;
a second VCO configured to output a second oscillation signal having a frequency proportional to a voltage level of the second sampling signal in response to a third clock signal and a fourth clock signal each having a frequency of half of a frequency of the second clock signal; and
a second counter configured to count the number of pulse signals in the second oscillation signal to output the second digital signal.

7. The ADC of claim 6 , wherein the second VCO comprising:
a second time delayer configured to delay a time of the second sampling signal by operating a plurality of inverters connected in a forward direction or a plurality of inverters connected in a reverse direction according to a clock signal applied by receiving the second sampling signal; and
a second oscillation frequency controller connected to the second time delayer and configured to control a frequency of the second oscillation signal using a frequency of the second sampling signal to output a voltage swing.

8. The ADC of claim 7 , wherein the second time delayer comprising:
a first delayer configured to delay the time of the second sampling signal by supplying a power supply voltage to the plurality of inverters, which are built-in and connected in the forward direction, and simultaneously operating the plurality of inverters when the third clock signal is applied, and
a second delayer configured to delay the time of the second sampling signal by supplying the power supply voltage to the plurality of inverters, which are built-in and connected in the reverse direction, and simultaneously operating the plurality of inverters when the fourth clock signal having a phase opposite to that of the third clock signal is applied.

9. The ADC of claim 8 , wherein at a time point at which the applied clock signal is changed from the third clock signal to the fourth clock signal:
a voltage of the second oscillation signal at a corresponding node is held; and
a phase of the second oscillation signal is changed and proceeds in a direction opposite to a direction in which the phase initially proceeds.

10. The ADC of claim 6 , wherein the second counter counts rising edges of the pulse signals in the second oscillation signal.

11. A band-pass analog-to-digital converter (ADC) using a bidirectional voltage-controlled oscillator (VCO), the ADC comprising:
a first converter configured to quantize an analog input signal according to a first clock signal to output a first digital signal;
a second converter configured quantize the analog input signal in a time-interleaving manner according to a second clock signal to output a second digital signal; and
a multiplexer configured to receive the first and second digital signals and select one of the two signals in response to the first clock signal to finally output a digital output signal,
wherein the first converter comprising:
a first sampling/holding part configured to sample a voltage level of the analog input signal at a rising edge of the first clock signal and hold the voltage level of the analog input signal until a next rising edge of the first clock signal to output a first sampling signal;
a first VCO configured to output a first oscillation signal having a frequency proportional to a voltage level of the first sampling signal in response to a third clock signal and a fourt

Assignees

• Korea Advanced Inst Sci & Tech

Inventors

• Cho Seonghwan
• Hong Junseok
• Park Pangi

Classifications

• H03M1/1215 Primary

  using time-division multiplexing · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/60 Primary

  with intermediate conversion to frequency of pulses · CPC title

• H03M1/0854

  of quantisation noise · CPC title

• H03M1/002

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title