Analog-to-digital converter with an increased resolution first stage

Patent metadata

Field	Value
Publication number	US-9735794-B1
Application number	US-201615395285-A
Country	US
Kind code	B1
Filing date	Dec 30, 2016
Priority date	Dec 30, 2016
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

One example includes a pipelined analog-to-digital converter device. The pipelined analog-to-digital converter device includes a capacitive digital-to-analog converter, a first analog-to-digital converter, and a second analog-to-digital converter. The capacitive digital-to-analog converter includes a capacitor comprised of a top plate and a bottom plate, the capacitive digital-to-analog converter sampling an analog input signal applied to the pipelined analog-to-digital converter device while the capacitor is grounded, holding the sampled analog input while the top plate is floated, and outputting a residue voltage. The second analog-to-digital converter is coupled to the top plate of the capacitor, the second analog-to-digital converter producing a second digital representation of voltage on the top plate of the capacitor after the top plate is floated, wherein the second digital representation represents fine bits produced by the first stage of the pipelined analog-to-digital converter device.

First claim

What is claimed is:

1. A pipelined analog-to-digital converter device, comprising:
a first stage comprising:
a capacitive digital-to-analog converter including a capacitor comprised of a top plate and a bottom plate, the capacitive digital-to-analog converter sampling an analog input signal applied to the pipelined analog-to-digital converter device on the bottom plate of the capacitor while the top plate of the capacitor is grounded, holding the sampled analog input while the top plate is floated, and outputting a residue voltage;
a first analog-to-digital converter coupled to the bottom plate of the capacitor, the first analog-to-digital converter producing a first digital representation of voltage on the bottom plate of the capacitor while the capacitor is grounded, wherein the first digital representation represents course bits produced by the first stage of the pipelined analog-to-digital converter device; and
a second analog-to-digital converter coupled to the top plate of the capacitor, the second analog-to-digital converter producing a second digital representation of voltage on the top plate of the capacitor after the top plate is floated, wherein the second digital representation represents fine bits produced by the first stage of the pipelined analog-to-digital converter device.

2. The pipelined analog-to-digital converter device according to claim 1 , further comprising:
a second stage comprising a third analog-to-digital converter coupled to an analog output of the capacitive digital-to-analog converter, the third analog-to-digital converter producing a third digital representation of the residue voltage from the first stage; and
a digital summer to sum the first, second, and third digital representations into a composite digital representation of the analog signal applied to the pipelined analog-to-digital converter device.

3. The pipelined analog-to-digital converter device according to claim 2 , wherein the second analog-to-digital converter is comprised of a linear voltage ladder coupled to a plurality of correction blocks, the plurality of correction blocks coupled to a plurality of comparators, respectively, wherein a feedback signal from an offset corrector is used by the correction blocks to modify thresholds of the comparators to correct for offset errors within the first and second digital representations received by the digital summer.

4. The pipelined analog-to-digital converter device according to claim 2 , further comprising an amplifier to amplify the residue voltage and to output the amplified residue voltage to the second stage.

5. The pipelined analog-to-digital converter device according to claim 2 , further comprising a feedback loop to feed back an offset-error correction signal from an offset corrector to the first analog-to-digital converter.

6. The pipelined analog-to-digital converter device according to claim 2 , further comprising a feedback loop to feed back an offset-error correction signal from an offset corrector to the second analog-to-digital converter.

7. The pipelined analog-to-digital converter device according to claim 1 , wherein the first and second analog-to-digital converters are flash analog-to-digital converters.

8. The pipelined analog-to-digital converter device according to claim 1 , wherein the first analog-to-digital converter produces four bits and the second analog-to-digital converter produces two bits.

9. A method of converting an analog signal to a digital signal, comprising:
sampling, on a bottom plate of a capacitor, an analog input signal applied to a pipelined analog-to-digital converter device while a top plate of the capacitor of a capacitive digital-to-analog converter is grounded;
converting a voltage on the bottom plate of the capacitor into a first digital representation, wherein the first digital representation represents course bits produced by a first stage of the pipelined analog-to-digital converter device; and

floating the top plate of the capacitor; and
converting a voltage on the top plate of the capacitor into a second digital representation, wherein the second digital representation represents fine bits produced by the first stage of the pipelined analog-to-digital converter device.

10. The method of converting an analog signal to a digital signal according to claim 9 , further comprising:
converting, after the first and second analog-to-digital converters produce the first and second digital representations, a residue voltage from the capacitive digital-to-analog converter into a third digital representation; and
digitally summing the first, second, and third digital representations into a composite digital representation of the analog signal applied to the device.

11. The method of converting an analog signal to a digital signal according to claim 10 , further comprising amplifying the residue voltage produced by the capacitive digital-to-analog converter prior to the conversion of the residue voltage.

12. The method of converting an analog signal to a digital signal according to claim 9 , further comprising modifying comparator thresholds of the first analog-to-digital converter to correct for offset errors within the first analog-to-digital converter.

13. The method of converting an analog signal to a digital signal according to claim 9 , further comprising modifying comparator thresholds of the second analog-to-digital converter to correct for offset errors within the second analog-to-digital converter.

14. The method according to claim 9 , further comprising producing two bits with the conversion of the voltage on the top plate of the capacitor.

15. The method according to claim 9 , further comprising producing four bits with the conversion of the voltage on the bottom plate of the capacitor.

16. A pipelined analog-to-digital converter device, comprising:
a first stage comprising:
a capacitive digital-to-analog converter including a capacitor comprised of a top plate and a bottom plate, the capacitive digital-to-analog converter sampling an analog input signal applied to the pipelined analog-to-digital converter device on the bottom plate of the capacitor while the top plate of the capacitor is grounded and holding the sampled analog input while the top plate is floated,
a first analog-to-digital converter coupled to the bottom plate of the capacitor, the first analog-to-digital converter producing a first digital representation of voltage on the bottom plate of the capacitor while the capacitor is grounded, wherein the first digital representation represents course bits produced by the first stage of the pipelined analog-to-digital converter device, and
a second analog-to-digital converter coupled to the top plate of the capacitor, the second analog-to-digital converter producing a second digital representation of voltage on the top plate of the capacitor after the top plate is floated, wherein the second digital representation represents fine bits produced by the first stage of the pipelined analog-to-digital converter device;

a second stage comprising a third analog-to-digital converter coupled to an analog output of the capacitive digital-to-analog converter, the third analog-to-digital converter producing a third digital representation of a residue voltage from the first stage; and
a digital summer to sum the first, second, and third digital representations into a composite digital representation of the analog signal applied to the pipelined analog-to-digital converter device.

17. The pipelined analog-to-digital converter device according to claim 16 , wherein the secon

Assignees

• Texas Instruments Inc

Inventors

• Paul Sabu
• Srinivasa Raghu Nandan

Classifications

• H03M1/002 Primary

  Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed · CPC title

• H03M1/001 Primary

  Analogue/digital/analogue conversion · CPC title

• H03M1/164

  the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence) · CPC title

• H03M1/0607 Primary

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title