Indium-gallium-nitride light emitting diodes with increased red-light quantum efficiency

Patent metadata

Field	Value
Publication number	US-11837683-B2
Application number	US-202117197493-A
Country	US
Kind code	B2
Filing date	Mar 10, 2021
Priority date	Mar 10, 2021
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

Exemplary processing methods of forming a semiconductor structure may include forming a nucleation layer on a semiconductor substrate. The methods may further include forming first, second, and third, gallium-and-nitrogen-containing regions on the nucleation layer. The first gallium-and-nitrogen-containing region may be porosified, without porosifying the second and third gallium-and-nitrogen containing regions. The methods may still further include forming a first active region on the porosified first gallium-and-nitrogen-containing region, and a second active region on the unporosified second gallium-and-nitrogen-containing region. The methods may yet also include forming a third active region on the unporosified third gallium-and-nitrogen-containing region.

First claim

The invention claimed is:

1. A semiconductor processing method comprising:
forming a nucleation layer on a semiconductor substrate;
forming first, second, and third gallium-and-nitrogen-containing regions on the nucleation layer;
porosifying the first gallium-and-nitrogen-containing region, without porosifiying the second and third gallium-and-nitrogen-containing regions;
forming a first active region on the porosified first gallium-and-nitrogen-containing region, and a second active region on the unporosified second gallium-and-nitrogen-containing region; and
forming a third active region on the unporosified third gallium-and-nitrogen-containing region.

2. The semiconductor processing method of claim 1 , wherein the first active region and the second active region are formed in a single deposition of an active region material on the semiconductor substrate.

3. The semiconductor processing method of claim 2 , wherein the active region material comprises an InGaN-containing material.

4. The semiconductor processing method of claim 1 , wherein the forming of the third active region further comprises forming one or more v-pits in the third active region.

5. The semiconductor processing method of claim 1 , wherein:
the first active region is characterized by a first peak light emission wavelength between a second peak light emission wavelength that characterizes the second active region and a third peak light emission wavelength that characterizes the third active region, and
the second peak light emission wavelength is less than or about 550 nm, and
the third peak light emission wavelength is greater than or about 600 nm.

6. The semiconductor processing method of claim 1 , wherein the method further comprises:
forming a first reflection layer on the first, second, and third active regions;
removing a portion of the first reflection layer from the third active region; and
forming a second reflection layer over the first, second, and third active regions.

7. The semiconductor processing method of claim 6 , wherein the first reflection layer comprises aluminum and the second reflection layer comprises copper.

8. A semiconductor processing method comprising:
forming first, second, and third gallium-and-nitrogen-containing regions;
depositing an active region material on the first and second gallium-and-nitrogen-containing-regions, wherein the active region material is formed into a first active region on the first gallium-and-nitrogen-containing region, and a second active region on the second gallium-and-nitrogen-containing region;
forming a third active region on the third gallium-and-nitrogen-containing region;
forming a first reflection layer on the first, second, and third active regions;
removing a portion of the first reflection layer from the third active region; and
forming a second reflection layer over the first, second, and third active regions.

9. The semiconductor processing method of claim 8 , wherein the method further comprises forming a transparent conductive layer on the first, second, and third active regions before the forming of the first reflection layer on the first, second, and third active regions.

10. The semiconductor processing method of claim 8 , wherein the transparent conductive layer comprises indium-tin-oxide.

11. The semiconductor processing method of claim 8 , wherein the first reflection layer comprises aluminum, and the second reflection layer comprises copper.

12. The semiconductor processing method of claim 8 , wherein the method further comprises porosifying the first gallium-and-nitrogen-containing region without porosifiying the second and third gallium-and-nitrogen-containing regions.

13. The semiconductor processing method of claim 8 , wherein the forming of the third active region further comprises forming one or more v-pits in the third active region.

14. The semiconductor processing method of claim 8 , wherein:
the first active region is characterized by a first peak light emission wavelength between a second peak light emission wavelength that characterizes the second active region and a third peak light emission wavelength that characterizes the third active region, and
the second peak light emission wavelength is less than or about 550 nm, and
the third peak light emission wavelength is greater than or about 600 nm.

15. A semiconductor structure comprising:
a first InGaN-containing active region on a porosified first gallium-and-nitrogen-containing region;
a second InGaN-containing active region on an unporosified second gallium-and-nitrogen-containing region; and
a third InGaN-containing active region on an unporosified third gallium-and-nitrogen-containing layer,
wherein the first active region is characterized by a first peak light emission wavelength between a second peak light emission wavelength that characterizes the second active region and a third peak light emission wavelength that characterizes the third active region, and
the second peak light emission wavelength is less than or about 550 nm, and
the third peak light emission wavelength is greater than or about 600 nm.

16. The semiconductor structure of claim 15 , wherein the first, second, and third, gallium-and-nitrogen-containing regions contact a nucleation layer comprising aluminum nitride, niobium nitride, titanium nitride, or hafnium nitride.

17. The semiconductor structure of claim 15 , wherein the first InGaN-containing active region and the second InGaN-containing active region are formed from a single deposition of InGaN-containing material.

18. The semiconductor structure of claim 15 , wherein the third InGaN-containing active region comprises one or more v-pits.

19. The semiconductor structure of claim 15 , wherein the semiconductor structure further comprises a first reflection layer comprising aluminum on the first and second active regions, and a second reflection layer comprising copper on the third active region.

20. The semiconductor structure of claim 19 , wherein the semiconductor structure further comprises a transparent conductive layer positioned between the active regions and the reflection layers.

Assignees

• Applied Materials Inc

Inventors

• Chudzik Michael
• Khoury Michel
• Batres Max

Classifications

• H10W90/00

  Package configurations · CPC title

• H10P72/0454

  surrounding a central transfer chamber · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/38

  characterised by treatments done after the formation of the materials · CPC title

• H10P14/272

  using mask materials other than SiO2 or SiN · CPC title