Array substrate and display panel

Patent metadata

Field	Value
Publication number	US-11837608-B2
Application number	US-202217714458-A
Country	US
Kind code	B2
Filing date	Apr 6, 2022
Priority date	Apr 15, 2020
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

An array substrate and a display panel. The array substrate includes: a substrate having a display region and a non-display region surrounding the display region. The non-display region includes a first sub-region extending in a first direction, a second sub-region extending in a second direction, and a third sub-region connecting the first sub-region with the second sub-region, and the third sub-region extends in an arc shape, and the first sub-region comprises a binding region; a plurality of signal lines extending in the display region; a plurality of circuit modules located on the substrate; and a plurality of fan-out lines located in the non-display region. Each of the fan-out lines is electrically connected to a corresponding one of the circuit modules and extends to the binding region.

First claim

What is claimed is:

1. An array substrate, comprising:
a substrate having a display region and a non-display region surrounding the display region, the non-display region comprising a first sub-region extending in a first direction, a second sub-region extending in a second direction intersecting with the first direction, and a third sub-region connecting the first sub-region with the second sub-region, and the third sub-region extending in an arc shape, and the first sub-region comprising a binding region;
a plurality of signal lines extending in the display region, each of the signal lines extending along the second direction;
a plurality of circuit modules located on the substrate, wherein at least part of the circuit modules are located between the display region and the binding region, each of the circuit modules is electrically connected to at least two of the signal lines, a part of the circuit modules are arranged in the first sub-region along the first direction, and another part of the circuit modules are arranged in an array in the third sub-region along an arc-shaped extending direction of the third sub-region;
a plurality of fan-out lines located in the non-display region, wherein each of the fan-out lines is electrically connected to a corresponding one of the circuit modules and extends to the binding region, and
a plurality of control lines configured to control conductions between the fan-out lines and corresponding signal lines, wherein:
each of the circuit modules comprises a demultiplexer, the demultiplexer comprises two or more first transistors, each of the first transistors comprises a first gate, a first electrode and a second electrode, and in the demultiplexer, the first gates of the first transistors are respectively electrically connected to the control lines, the first electrodes of the first transistors are respectively electrically connected to the corresponding signal lines, and the second electrodes of the first transistors extend to the binding region through a same fan-out line, and/or
each of the circuit modules comprises a detection module, the detection module comprises two or more second transistors, each of the second transistors comprises a second gate, a third electrode and a fourth electrode, and in the detection module, the second gates of the second transistors are respectively electrically connected to the control lines, the third electrodes of the second transistors are respectively electrically connected to the corresponding signal lines of a same signal type, and the fourth electrodes of the second transistors extend to the binding region through the fan-out line.

2. The array substrate according to claim 1 , wherein the circuit modules located in the first sub-region are adjacent to the circuit modules located in the third sub-region.

3. The array substrate according to claim 1 , wherein each of the circuit modules comprises a first side, and a pitch between two first sides of two adjacent circuit modules located in the first sub-region is the same as a pitch between two first sides of two adjacent circuit modules located in the third sub-region.

4. The array substrate according to claim 1 , further comprising:
wherein in the third sub-region, the control lines connected between adjacent ones of the circuit modules extend in an arc shape.

5. The array substrate according to claim 1 , further comprising:
a plurality of driving circuits disposed on the substrate, wherein the driving circuits are located in the non-display region and are located on at least one side of the display region along the first direction, and a part of the driving circuits are arranged in the second sub-region along the second direction, and another part of the driving circuits are arranged in an array in the third sub-region along the arc-shaped extending direction of the third sub-region.

6. The array substrate according to claim 5 , wherein in the third sub-region, the circuit modules are located between the driving circuits and the display region.

7. The array substrate according to claim 5 , further comprising:
a plurality of signal buses disposed on the substrate, wherein the plurality of signal buses are electrically connected to the driving circuits and extend to the binding region, and
in a thickness direction of the array substrate, an orthographic projection of the plurality of signal buses and an orthographic projection of the plurality of fan-out lines are not overlapped.

8. The array substrate according to claim 5 , wherein in a radial direction of the third sub-region of the arc shape, the driving circuits and the circuit modules are not overlapped.

9. The array substrate according to claim 1 , wherein each of the circuit modules comprises the demultiplexer and the detection module, and the detection module is located on a side of the demultiplexer close to the display region.

10. The array substrate according to claim 1 , wherein each of the circuit modules comprises the detection module, and the array substrate further comprises:
a plurality of binding terminals located in the binding region,
wherein in a same second transistor, the fourth electrode is electrically connected to a corresponding binding terminal through the fan-out line, and the signal line connected to the third electrode has a same signal type as the binding terminal.

11. A display panel comprising the array substrate according to claim 1 .

Assignees

• Kunshan Govisionox Optoelectronics Co Ltd

Inventors

• Qin Xu
• Chang Miao
• Zhang Lu
• Hu Siming
• Han Zhenzhen

Classifications

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H01L27/124 Primary

  Electricity · mapped topic

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title