Stacked dies and methods for forming bonded structures

Patent metadata

Field	Value
Publication number	US-11837596-B2
Application number	US-202218145261-A
Country	US
Kind code	B2
Filing date	Dec 22, 2022
Priority date	May 19, 2016
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

First claim

What is claimed is:

1. A method of forming a multi-layer bonded structure, the method comprising:
forming a first die layer over a carrier, wherein the forming the first die layer comprises:
directly bonding a first integrated device die to the carrier without an intervening adhesive;
applying a first protective material over the first integrated device die bonded to the carrier;
after the applying the first protective material, thinning the first integrated device die from a first thickness of greater than 40 microns to a second thickness of less than 40 microns; and
preparing a bonding surface of the first die layer, the bonding surface comprising a first non-conductive region and a first conductive region; and

forming a second die layer over the first die layer, wherein the forming the second die layer comprises:
directly bonding a second integrated device die to the bonding surface of the first die layer without an intervening adhesive, wherein the second integrated device die has a second non-conductive region and a second conductive region, and wherein the directly bonding the second integrated device die to the first die layer comprises directly bonding the second non-conductive region to the first non-conductive region and directly bonding the second conductive region to the first conductive region; and
applying a second protective material over the second integrated device die bonded to the first die layer and over the first protective material.

2. The method of claim 1 , further comprising providing the first non-conductive region of the bonding surface over a backside of the first integrated device die after thinning the first integrated device die.

3. The method of claim 2 , wherein the directly bonding the first integrated device die to the carrier comprises directly bonding an active side of the first integrated device die to the carrier, the active side opposite the backside.

4. The method of claim 3 , wherein the thinning the first integrated device die exposes through substrate vias (TSVs) in the first integrated device die.

5. The method of claim 1 , wherein after the thinning, the first integrated device die has a thickness less than 30 microns.

6. The method of claim 5 , wherein after the thinning, the first integrated device die has a thickness less than 20 microns.

7. The method of claim 1 , wherein the applying the first protective material comprises forming a first protective layer over the first integrated device die and forming a second protective layer over the first protective layer.

8. The method of claim 7 , wherein the forming the second protective material comprises forming a third protective layer over the second integrated device die and forming a fourth protective layer over the third protective layer.

9. The method of claim 1 , wherein the applying the first protective material comprises applying a thickness of the first protective material that is greater than the second thickness of the first integrated device die.

10. The method of claim 9 , wherein the applying the second protective material comprises applying a thickness of the second protective material that is greater than a final thickness of the second integrated device die after thinning the second integrated device die.

11. The method of claim 1 , wherein the applying the first protective material comprises depositing a silicon-containing, inorganic dielectric material over the first integrated device die.

12. The method of claim 1 , further comprising thinning the second integrated device die after the applying the second protective material.

13. The method of claim 1 , wherein the forming the second die layer comprises directly bonding a third die to the bonding surface of the first die layer without an intervening adhesive.

14. The method of claim 13 , wherein the forming the second die layer comprises applying the second protective material over the third die and filling a gap between the second integrated device die and the third die with the second protective material.

15. The method of claim 14 , wherein the forming the first die layer comprises directly bonding a fourth integrated device die to the carrier adjacent the first integrated device die without an intervening adhesive.

16. The method of claim 15 , further comprising singulating the multi-layer bonded structure into a plurality of integrated device packages.

17. The method of claim 1 , wherein the carrier comprises a redistribution layer (RDL).

18. The method of claim 1 , further comprising providing a redistribution layer (RDL) between the second protective material and the first protective material.

19. The method of claim 1 , further comprising removing at least a portion of the carrier.

20. A method of forming a multi-layer bonded structure, comprising:
forming a first device layer comprising a first integrated device die, wherein the forming the first device layer comprises:
applying a first protective material over sidewalls of the first integrated device die;
after the applying the first protective material, thinning the first integrated device die; and
preparing a bonding surface of the first device layer, the bonding surface comprising a first non-conductive region and a first conductive region; and

forming a second device layer over the first device layer, wherein the forming the second device layer comprises:
directly bonding a second integrated device die to the bonding surface of the first device layer without an intervening adhesive, wherein the second integrated device die has a second non-conductive region and a second conductive region, and wherein the directly bonding the second integrated device die to the first device layer comprises directly bonding the second non-conductive region to the first non-conductive region and directly bonding the second conductive region to the first conductive region;
applying a second inorganic protective material over the second integrated device die bonded to the first device layer;
after the applying the second inorganic protective material, thinning the second integrated device die; and
preparing a bonding surface of the second device layer comprising a third non-conductive region suitable for direct bonding to a non-conductive region of an additional element.

21. The method of claim 20 , further comprising directly bonding the additional element to the bonding surface of the second device layer.

22. The method of claim 20 , further comprising annealing the second integrated device die and the first device layer.

23. The method of claim 20 , wherein the thinning the first integrated device die comprises thinning the first integrated device die from a first thickness of greater than 40 microns to a second thickness of less than 40 microns.

24. A method of forming a bonded structure, the method comprising:
providing a first inorganic dielectric material including a first layer on a side surface of a first die and a second layer on the first layer, the first die including a through substrate via (TSV);
providing a dielectric layer over the first die and the first inorganic dielectric material;
providing a conductive material in a cavity of the dielectric layer, the conductive material electrically connected to the TSV;
directly bonding a second die to the dielectric layer without an adhesive, the second die including a conductive region directly bonded to the conductive material without an adhesive; and

Assignees

• Adeia Semiconductor Bonding Technologies Inc

Inventors

• Uzoh Cyprian Emeka
• Sitaram Arkalgud R
• Enquist Paul

Classifications

• H10P72/70

  for supporting or gripping · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10W90/722

  between stacked chips · CPC title