Neural processing unit and electronic apparatus including the same

Patent metadata

Field	Value
Publication number	US-11836606-B2
Application number	US-202016778168-A
Country	US
Kind code	B2
Filing date	Jan 31, 2020
Priority date	Oct 30, 2019
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

A storage device is provided including an interface circuit configured to receive application information from a host; a field programmable gate array (FPGA); a neural processing unit (NPU); and a central processing unit (CPU) configured to select a hardware image from among a plurality of hardware images stored in a memory using the application information, and reconfigure the FPGA using the selected hardware image. The NPU is configured to perform an operation using the reconfigured FPGA.

First claim

What is claimed is:

1. A storage device comprising:
an interface circuit configured to receive application information from a host;
a field programmable gate array (FPGA) including a dynamic region and a static region;
a neural processing unit (NPU); and
a central processing unit (CPU) configured to select a hardware image from among a plurality of hardware images stored in a memory using the application information, and reconfigure the dynamic region of the FPGA through the selected hardware image,
wherein the NPU is configured to perform a first operation using the reconfigured dynamic region of the FPGA,
wherein the static region of the FPGA is configured to perform a second operation without loading the hardware image when the second operation is performed more frequently than the first operation and the second operation is a non-linear operation.

2. The storage device of claim 1 , wherein the selected hardware image is associated with a selected one of a plurality of different machine learning algorithms and the application information indicates the machine learning algorithm to select.

3. The storage device of claim 2 , wherein the reconfigured FPGA performs a pre-computation on data input to the neural processing unit for the selected machine learning algorithm to generate a value and the neural processing unit performs the selected machine learning algorithm on the value using weight data stored in the memory to generate a result.

4. The storage device of claim 3 , further comprising a multiply-accumulate calculator (MAC) configured to perform the selected machine learning algorithm on the value using the weight data to generate the result.

5. The storage device of claim 2 , wherein the NPU performs the selected machine learning algorithm on input data using weight data stored in the memory to generate a value, and the reconfigured FPGA performs a post-computation on the value to generate a result.

6. The storage device of claim 2 , wherein the reconfigured FPGA performs the selected machine learning algorithm on input data using weight data stored in the memory to generate a result.

7. The storage device of claim 1 , wherein the memory is a static random access memory (SRAM) or a register located within the NPU.

8. The storage device of claim 1 , further comprising a non-volatile memory controller connected to the memory and the memory is located outside a controller including the NPU, the CPU, and the FPGA.

9. A method of operating a neural processing unit (NPU), the method comprising:
receiving, by the NPU, application information and data from a host device;
selecting, by the NPU, one of a plurality of hardware images from a memory by referencing an entry of a mapping table using the application information;
loading, by the NPU, the selected hardware image to a field programmable gate array (FPGA) within the NPU to configure the FPGA; and
performing, by the NPU, a machine learning algorithm associated with the application information on the data to generate a result using the configured FPGA.

10. The method of claim 9 , wherein the loading configures a dynamic region of the FPGA using the selected hardware image and maintains a static region of the FPGA.

11. The method of claim 9 , wherein the performing comprises:
loading weight data from the memory;
executing the machine learning algorithm on the data using the loaded weight data stored to generate a value; and
directing the configured FPGA to perform a post-computation on the value to generate the result.

12. The method of claim 9 , wherein the performing comprises:
loading weight data from the memory;
directing the configured FPGA to perform a pre-computation on the data to generate a value; and
performing the machine learning algorithm on the value using the loaded weight data to generate the result.

13. A storage device comprising:
an interface circuit configured to receive application information from a host;
a field programmable gate array (FPGA);
a neural processing unit (NPU); and
a central processing unit (CPU) configured to select a hardware image from among a plurality of hardware images stored in a memory using the application information, and reconfigure the FPGA using the selected hardware image,
wherein the NPU is configured to perform a first operation using the reconfigured FPGA when a work load of the NPU is higher than a threshold, and performs a second operation different from the first operation without using the reconfigured FPGA when the work load is not higher than the threshold.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lim Jin Soo
• Seol Chang Kyu
• Jang Jae Hun
• So Hye Jeong
• Son Hong Rak
• Yoon Pil Sang

Classifications

• G06F40/40

  Processing or translation of natural language (natural language analysis G06F40/20; semantic analysis G06F40/30) · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G06N20/00

  Machine learning · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title