Non-volatile, solid-state memory configured to perform logical combination of two or more blocks sharing series-connected bit lines

Patent metadata

Field	Value
Publication number	US-9727459-B2
Application number	US-201414466143-A
Country	US
Kind code	B2
Filing date	Aug 22, 2014
Priority date	Aug 22, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.

First claim

What is claimed is:

1. A method, comprising:
storing a first and second data representation in first and second blocks of a non-volatile, solid-state memory, the first and second blocks sharing series-connected bit lines;
selecting the first and second blocks and deselecting other blocks of the non-volatile, solid-state memory that share the bit lines; and
reading the bit lines to determine a union of the first and second data representations, a union the union comprising a Bloom filter;
performing a bitwise comparison of input data with the Bloom filter; and
returning the comparison as a search result of the Bloom filter.

2. The method of claim 1 , wherein the first and second blocks comprise first and second word lines.

3. The method of claim 1 , further comprising copying the combination to a third block of the non-volatile, solid-state memory.

4. The method of claim 1 , wherein the first and second data representation are sparse representations.

5. The method of claim 4 , wherein the input data comprises a sparse input.

6. The method of claim 5 , wherein the comparison is false only when 1-bits in the sparse input match a corresponding 0-bit in the union.

7. A method, comprising:
storing data representations in blocks of non-volatile memory that share series-connected bit lines;
reading first bits of a first of the blocks into a register of a memory controller of the non-volatile memory; and
reading second bits of a second of the blocks into the register, wherein the register performs a bitwise combination of the first bits with respective ones of the second bits.

8. The method of claim 7 , further comprising using the bitwise combination in a bitwise comparison.

9. The method of claim 8 , wherein the bitwise comparison is false only when 1-bits of a comparison value match corresponding 0-bits in the bitwise combination.

10. The method of claim 7 , wherein the bitwise combination comprises a logical OR, and where the bitwise combination comprises a union of the first block and the second block.

11. The method of claim 7 , wherein the bitwise combination comprises a logical AND, and where the bitwise combination comprises an intersection of the first block and the second block.

12. A storage compute device, comprising:
non-volatile memory comprising a plurality of blocks that share series-connected bit lines, each block comprising a word line;
a controller logic coupled to the word lines and configured to simultaneously select a first set of two or more blocks and deselect other blocks of the plurality of blocks; and
a plurality of sense amplifiers coupled to read the bit lines to determine a union of data stored in the first set of blocks, the union representing a neuron of a neural network;
performing a bitwise comparison of input data with the union; and
returning the comparison as a categorization of the input data by the neural network.

13. A storage compute device, comprising:
non-volatile memory comprising a plurality of blocks that share series-connected bit lines, each block comprising a word line;
a combinatorial register;
a comparison register;
a controller logic coupled to the word lines and configured to simultaneously select a first set of two or more blocks and deselect other blocks of the plurality of blocks; and
a plurality of sense amplifiers coupled to read the bit lines to determine a union of data stored in the first set of blocks, the controller logic further configured to:
store the union in the combinatorial register;
store an input in the comparison register;
perform a bitwise comparison between the combinatorial register to the comparison register; and
return a result of the comparison.

14. The storage compute device of claim 13 , wherein the bitwise comparison is false only when 1-bits of the comparison register match corresponding 0-bits of the combinatorial register.

15. The storage compute device of claim 13 , wherein the input comprises sparse data representations.

16. The storage compute device of claim 13 , wherein the union comprises one of a Bloom filter and a neural network.

17. The storage compute device of claim 12 , wherein the non-volatile memory comprises NAND flash memory.

18. The storage compute device of claim 17 , wherein the NAND flash memory comprises SLC memory.

19. The storage compute device of claim 12 , wherein the input data comprises sensory data.

20. The storage compute device of claim 12 , wherein the categorization is used to reinforce or de-emphasize neural connections of the neural network.

Assignees

• Seagate Technology Llc

Inventors

• Khoueir Antoine
• Goss Ryan James
• Trantham Jon
• Gomez Kevin
• Dropps Frank

Classifications

• G11C2211/5641

  Multilevel memory having cells with different number of storage levels · CPC title

• G11C15/046

  using non-volatile storage elements · CPC title

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G06F12/00

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

• G11C7/00

  Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) · CPC title