Floating-point division circuitry with subnormal support

Patent metadata

Field	Value
Publication number	US-11836459-B2
Application number	US-202117218041-A
Country	US
Kind code	B2
Filing date	Mar 30, 2021
Priority date	Mar 30, 2021
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

Techniques are disclosed relating to circuitry for floating-point division. In some embodiments, the circuitry is configured to generate a subnormal result for a division operation that divides a numerator by a denominator. The circuitry may include floating-point circuitry configured to perform a reciprocal operation to determine a normalized mantissa value for the reciprocal of a floating-point representation of the denominator. The circuitry may further include fixed-point circuitry configured to multiply a fixed-point representation of the normalized mantissa value for the reciprocal by a mantissa of the numerator to generate an initial value. Control circuitry may determine error data for the initial value and generate a final subnormal mantissa result for the division operation based on the error data and the initial value. Embodiments with multiple modes with different accuracy guarantees are disclosed.

First claim

What is claimed is:

1. An apparatus, comprising:
circuitry configured to generate a subnormal result for a division operation that divides a numerator by a denominator, comprising:
floating-point pipeline execution circuitry configured to perform a single reciprocal operation to determine a normalized mantissa value for a reciprocal of a floating-point representation of the denominator;
fixed-point pipeline execution circuitry that includes:
multiplier circuitry configured to, as part of performance of a single integer instruction by the fixed-point pipeline execution circuitry, multiply a fixed-point representation of the normalized mantissa value for the reciprocal by a mantissa of the numerator to generate an initial value;
error circuitry configured to determine, as part of performance of the single integer instruction, error data based on one or more bits that are shifted out in one or more shift operations performed by shift circuitry on the initial value, wherein the single integer instruction includes the normalized mantissa value for the reciprocal of the floating-point representation of the denominator, the numerator, and at least a portion of the denominator as input operands; and
selection circuitry configured to generate, as part of performance of the single integer instruction, a final subnormal mantissa result for the division operation, including to determine whether to increment the initial value based on the error data to generate the final subnormal mantissa result.

2. The apparatus of claim 1 , wherein the fixed-point pipeline execution circuitry is configured to:
determine the error data based on guard, sticky, and least significant bits of the output of one or more shift operations performed on the initial value; and
generate the final subnormal mantissa result by incrementing the initial value based on the error data.

3. The apparatus of claim 1 , wherein the fixed-point pipeline execution circuitry includes an increment circuit configured to increment the initial value.

4. The apparatus of claim 1 , wherein the floating-point pipeline execution circuitry and the fixed-point pipeline execution circuitry are further configured to generate a more precise subnormal result for another division operation than the final subnormal mantissa result for the division operation, based on execution of three or more instructions.

5. The apparatus of claim 4 , wherein the apparatus is configured to execute the single reciprocal operation and the single integer instruction using a smaller number of clock cycles than used to execute the three or more instructions.

6. The apparatus of claim 1 , wherein the single integer instruction further includes a flush-to-zero input operand; and
wherein the flush-to-zero input operand indicates whether to flush the final subnormal mantissa result to correctly-signed zero.

7. A non-transitory computer-readable medium having instructions stored thereon that are executable by a computing device to perform operations comprising:
generating a subnormal result for a division operation that divides a numerator by a denominator, including:
executing, by a floating-point unit, a single floating-point instruction to perform a reciprocal operation to determine a normalized mantissa value for a reciprocal of a floating-point representation of the denominator;
executing, by a fixed-point unit, a single integer instruction to:
multiply, by integer multiplier circuitry, a fixed-point representation of the normalized mantissa value for the reciprocal by a mantissa of the numerator to generate an initial value;
determine, by error circuitry, error data based on one or more bits that are shifted out by shift circuitry in one or more shift operations performed on the initial value, wherein the single integer instruction includes the normalized mantissa value for the reciprocal of the floating-point representation of the denominator, the numerator, and at least a portion of the denominator as input operands; and
generate, by selection circuitry, a final subnormal mantissa result for the division operation, including to determine whether to increment the initial value based on the error data to generate the final subnormal mantissa result.

8. The non-transitory computer-readable medium of claim 7 , wherein determining the error data is based on guard, sticky, and least significant bits of the output of one or more shift operations performed on the initial value; and
generating the final subnormal mantissa result includes incrementing the initial value based on the error data.

9. The non-transitory computer-readable medium of claim 7 , the operations further comprising:
generating, by the floating-point unit and the fixed-point unit, based on execution of three or more instructions, a precise subnormal result for another division operation; and
wherein the precise subnormal result is more accurate relative to the final subnormal mantissa result.

10. The non-transitory computer-readable medium of claim 9 , wherein the executing the single floating-point instruction and the single integer instruction uses a smaller number of clock cycles than used in execution of the three or more instructions.

11. The non-transitory computer-readable medium of claim 7 , wherein the single integer instruction further includes a flush-to-zero input operand; and
wherein the flush-to-zero input operand indicates whether to flush the final subnormal mantissa result to correctly-signed zero.

12. A non-transitory computer-readable medium having stored thereon design information that specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the hardware integrated circuit according to the design, wherein the design information specifies that the hardware integrated circuit includes:
circuitry configured to generate a subnormal result for a division operation that divides a numerator by a denominator, comprising:
floating-point pipeline execution circuitry configured to perform a single reciprocal operation to determine a normalized mantissa value for a reciprocal of a floating-point representation of the denominator;
fixed-point pipeline execution circuitry that includes:
multiplier circuitry configured to, as part of performance of a single integer instruction by the fixed-point pipeline execution circuitry, multiply a fixed-point representation of the normalized mantissa value for the reciprocal by a mantissa of the numerator to generate an initial value;
error circuitry configured to determine, as part of performance of the single integer instruction, error data based on one or more bits that are shifted out in one or more shift operations performed by shift circuitry on the initial value, wherein the single integer instruction includes the normalized mantissa value for the reciprocal of the floating-point representation of the denominator, the numerator, and at least a portion of the denominator as input operands; and
selection circuitry configured to generate, as part of performance of the single integer instruction, a final subnormal mantissa result for the division operation, including to determine whether to increment the initial value based on the error data to generate the final subnormal mantissa result.

13. The non-transitory computer-readable medium of claim 12 , wherein the fixed-point pipeline execution circuitry is configured to:
determine the error data based on guard, sticky, and least significant bits of the output of one or more shift operations performed on the initial value

Assignees

• Apple Inc

Inventors

• Wang Liang-Kai
• Ollmann Ian R
• Tai Anthony Y

Classifications

• G06F7/4873 Primary

  Dividing · CPC title

• G06F7/4876

  Multiplying · CPC title

• G06F7/49984

  Rounding away from zero · CPC title