System and method for enabling clock stretching during overclocking in response to voltage droop

Patent metadata

Field	Value
Publication number	US-11835998-B2
Application number	US-202117362231-A
Country	US
Kind code	B2
Filing date	Jun 29, 2021
Priority date	Jun 29, 2021
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

Methods and apparatuses control the clock rate of a processing unit. The methods and apparatus control the clock rate by generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking. The methods include: receiving an analog voltage supply in response to detecting overclocking in the processing unit; dynamically sensing measurements of an output voltage from a voltage generator based on the received analog voltage supply; determining characteristics of a voltage droop in the output voltage based on the dynamically sensed output voltage measurements; determining a frequency adjustment for the clock rate of the processing unit based on the determined characteristics of the voltage droop; and generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking.

First claim

What is claimed is:

1. A method of controlling a clock rate of a processing unit, comprising:
receiving an analog voltage supply to a voltage generator in response to detecting overclocking in the processing unit;
dynamically sensing measurements of an output voltage from the voltage generator based on the received analog voltage supply;
determining characteristics of a voltage droop in the output voltage based on the dynamically sensed output voltage measurements;
determining a frequency adjustment for the clock rate of the processing unit based on the determined characteristics of the voltage droop; and
generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking.

2. The method of claim 1 , wherein the frequency adjustment is determined to compensate for the voltage droop based on the characteristics of the voltage droop.

3. The method of claim 1 , wherein the characteristics of the voltage droop includes a change in the output voltage and a rate of change of the output voltage.

4. The method of claim 1 , wherein the output clock rate is further adjusted based on the output voltage.

5. The method of claim 1 , wherein the overclocking in the processing unit is configured to be detected at initial system startup.

6. The method of claim 1 , wherein the overclocking in the processing unit is configured to be detected in response to an adjustment request from a system firmware operably coupled with the processing unit.

7. The method of claim 1 , wherein the overclocking in the processing unit is configured to be detected in response to an adjustment request from an user input.

8. The method of claim 1 , wherein the overclocking in the processing unit is configured to be detected in response to an adjustment request based on a feedback from the processing unit.

9. The method of claim 8 , wherein the adjustment request is based on the generated output clock rate.

10. A clock generator comprising:
a voltage sensor configured to:
receive an analog voltage supply to a voltage generator, and
dynamically sense measurements of an output voltage from the voltage generator based on the received analog voltage supply;

an oscillation adjustment module operably coupled with the voltage sensor, the oscillation adjustment module configured to:
receive an indication of overclocking in a processing unit,
receive the dynamically sensed output voltage measurements from the voltage sensor,
determine characteristics of a voltage droop in the output voltage based on the dynamically sensed output voltage measurements, and
determine a frequency adjustment for the clock rate of the processing unit based on the determined characteristics of the voltage droop; and

a clock oscillator operably coupled with the oscillation adjustment module, the clock oscillator configured to:
receive the frequency adjustment from the oscillation adjustment module, and generate an output clock rate based on the determined frequency adjustment
such that the processing unit maintains the overclocking.

11. The clock generator of claim 10 , wherein the frequency adjustment is determined to compensate for the voltage droop based on the characteristics of the voltage droop.

12. The clock generator of claim 10 , wherein the characteristics of the voltage droop includes a change in the output voltage and a rate of change of the output voltage.

13. The clock generator of claim 10 , further comprising a clock buffer operably coupled with the clock oscillator, the clock buffer configured to:
receive the output clock rate from the clock oscillator,
receive the output voltage from the voltage generator, and
adjust the received output clock rate based on the output voltage.

14. The clock generator of claim 10 , wherein the overclocking in the processing unit is configured to be detected in response to an adjustment request based on a feedback from the processing unit.

15. The clock generator of claim 14 , wherein the adjustment request is based on the generated output clock rate.

16. A system comprising:
a voltage generator configured to generate an output voltage based on an analog voltage supply;
at least one processing unit configured to receive the output voltage from the voltage generator;
a controller; and
a clock generator operably coupled with the voltage generator, the at least one processing unit, and the controller, the clock generator configured to:
receive the analog voltage supply from the voltage generator and an indication of overclocking from the controller,
dynamically sense measurements of the output voltage from the voltage generator based on the received analog voltage supply,
determine characteristics of a voltage droop in the output voltage based on the dynamically sensed output voltage measurements,
determine a frequency adjustment for a clock rate of the processing unit based on the determined characteristics of the voltage droop,
generate an output clock rate based on the determined frequency adjustment, such that the processing unit maintains the overclocking.

17. The system of claim 16 , wherein the voltage generator further comprises a voltage supply and a voltage regulator, the controller comprises an overclock determination module configured to:
determine the overclocking in the processing unit based on measured frequency and frequency adjustment values detected from the processing unit,
send a voltage supply signal to the voltage supply to change the analog voltage supply,
send an output voltage signal to the voltage regulator to change the output voltage, and
send overclock parameters to the clock generator reflecting the changes in the analog voltage supply and the output voltage.

18. The system of claim 16 , wherein the frequency adjustment is determined to compensate for the voltage droop based on the characteristics of the voltage droop.

19. The system of claim 16 , wherein the characteristics of the voltage droop includes a change in the output voltage and a rate of change of the output voltage.

20. The system of claim 16 , the clock generator further configured to adjust the received output clock rate based on the output voltage.

21. The system of claim 16 , wherein the controller is configured to set the overclocking at an initial startup of the system.

22. The system of claim 16 , wherein the controller is configured to set the overclocking in response to an adjustment request for increased performance from the processing unit.

23. The system of claim 16 , wherein the controller is configured to set the overclocking in response to an adjustment request from an user input.

24. The system of claim 16 , wherein the controller is configured to set the overclocking in response to an adjustment request based on a feedback from the processing unit.

25. The system of claim 24 , wherein the adjustment request is based on the generated output clock rate.

Assignees

• Advanced Micro Devices Inc

Inventors

• Mehra Amitabh
• Ahrens Jerry A
• Harwani Anil
• Born Richard Martin
• Robinson Dirk J
• Alverson William R
• Knight Joshua Taylor

Classifications

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/28 Primary

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• H03K5/00006

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title