Clock Adjustment For Voltage Droop

Patent metadata

Field	Value
Publication number	US-2018018009-A1
Application number	US-201615208388-A
Country	US
Kind code	A1
Filing date	Jul 12, 2016
Priority date	Jul 12, 2016
Publication date	Jan 18, 2018
Grant date	—

Abstract

A processor adjusts frequencies of one or more clock signals in response to a voltage droop at the processor. The processor generates at least one clock signal by generating a plurality of base clock signals, each of the base clock signals having a common frequency but a different phase. The processor also generates a plurality of enable signals, wherein each enable signal governs whether a corresponding one of the base clock signals is used to generate the clock signal. The enable signals therefore determine the frequency of the clock signal. In response to detecting a voltage droop, the processor adjusts the enable signals used to generate the clock signal, thereby reducing the frequency of the clock signal droop.

First claim

What is claimed is:

1 . A method comprising:
in response to detecting a voltage drop at a processor, modifying a first set of enable signals to generate a modified first set of enable signals; and generating a first clock signal based on the modified first set of enable signals.

2 . The method of claim 1 , wherein modifying the first set of enable signals comprises:
modifying the first set of enable signals to change a frequency of the first clock signal from a first frequency to a second frequency.

3 . The method of claim 2 , wherein the second frequency is less than the first frequency.

4 . The method of claim 1 , further comprising:
after detecting the voltage drop at the processor, in response to detecting a voltage increase at the processor, modifying the modified first set of enable signals to generate a modified second set of enable signals; and generating the first clock signal based on the modified second set of enable signals.

5 . The method of claim 1 , wherein generating the first clock signal comprises:
selecting a plurality of clock signals based on the modified first set of enable signals; and logically combining the selected plurality of clock signals to generate the first clock signal.

6 . The method of claim 1 , further comprising:
in response to detecting the voltage drop at the processor, modifying a second set of enable signals to generate a modified second set of enable signals; and generating a second clock signal based on the modified second set of enable signals.

7 . The method of claim 6 , wherein:
generating the first clock signal comprises generating the first clock signal to have a first frequency; and generating the second clock signal comprises generating the second clock signal to have a second frequency different from the first frequency.

8 . A method, comprising generating a first set of enable signals;
generating a first clock signal at a first frequency based on the first set of enable signals; providing the first clock signal at the first frequency to a processor; and in response to detecting a voltage drop at the processor, modifying the first set of enable signals to change a frequency of the first clock signal from the first frequency to a second frequency, the second frequency different from the first frequency.

9 . The method of claim 8 , further comprising:
in response to detecting a voltage increase at the processor after the voltage drop, modifying the first set of enable signals to change the frequency of the first clock signal from the second frequency to the first frequency.

10 . The method of claim 8 , further comprising:
in response to detecting a voltage increase at the processor after the voltage drop, modifying the first set of enable signals to change the frequency of the first clock signal from the second frequency to a third frequency, the third frequency different from the first frequency and from the second frequency.

11 . The method of claim 8 , further comprising:
providing the first clock signal to a cache associated with the processor.

12 . The method of claim 8 , further comprising:
generating a second set of enable signals; generating a second clock signal at a third frequency based on the second set of enable signals; providing the second clock signal at the second frequency to the processor; and in response to detecting the voltage drop at the processor, modifying the first set of enable signals to change a frequency of the second clock signal from the third frequency to a fourth frequency, the fourth frequency different from the third frequency.

13 . The method of claim 8 , wherein generating the first clock signal comprises:
selecting, based on the first set of enable signals, a subset of clock signals from a plurality of clock signal; and combining the selected plurality of clock signals to generate the first clock signal.

14 . A processor comprising:
a voltage detection module to detect a voltage drop at the processor; a first clock module to receive a first set of enable signals and a first plurality of clock signals, the first clock module to generate a first clock signal based on the first set of enable signals and the plurality of clock signals; and a stretch control module to modify the first set of enable signals in response to the voltage detection module indicating the voltage drop.

15 . The processor of claim 14 , wherein the stretch control module is to:
modify the first set of enable signals to change a frequency of the first clock signal from a first frequency to a second frequency.

16 . The processor of claim 15 , wherein the second frequency is less than the first frequency.

17 . The processor of claim 14 , wherein the stretch control module is to:
in response to the voltage detection module indicating an increase in the voltage at the processor, modifying the modified first set of enable signals to generate a modified second set of enable signals.

18 . The processor of claim 14 , wherein the first clock module is to:
select a subset of the plurality of clock signals based on the first set of enable signals; and logically combine the selected plurality of clock signals to generate the first clock signal.

19 . The processor of claim 14 , further comprising:
a second clock module to receive a second set of enable signals and the first plurality of clock signals, the first clock module to generate a second clock signal based on the second set of enable signals and the plurality of clock signals; and a stretch control module to modify the second set of enable signals in response to the voltage detection module indicating the voltage drop.

20 . The processor of claim 19 , wherein:
the first clock module is to generate the first clock signal to have a first frequency; and the second clock module is to generate the second clock signal to have a second frequency different from the first frequency.

Assignees

• Advanced Micro Devices Inc

Inventors

• Kommrusch Steven
• Mehra Amitabh
• Born Richard Martin
• Young Bobby D

Classifications

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/305

  in the event of power-supply fluctuations · CPC title

• G06F11/0796 Primary

  Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element · CPC title

• G06F11/3058

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title