Display substrate having dummy pixel, display panel, and electronic device

Patent metadata

Field	Value
Publication number	US-11835829-B2
Application number	US-202017280667-A
Country	US
Kind code	B2
Filing date	Sep 23, 2020
Priority date	Nov 28, 2019
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

A display substrate is provided, including: a base substrate; a display area, and a peripheral area surrounding the display area on the base substrate, where a dummy pixel unit and a dummy data line are located in the peripheral area. The dummy pixel unit includes a thin film transistor including a first electrode and a second electrode. The first electrode is one of a source electrode and a drain electrode and is electrically connected to the dummy data line, and the second electrode is another of the source electrode and the drain electrode and includes a first portion and a second portion separated by a first opening. A display panel including the display substrate and an electronic device including the display substrate or the display panel are further provided.

First claim

What is claimed is:

1. A display substrate, comprising:
a base substrate; and
a display area and a peripheral area surrounding the display area on the base substrate,
wherein a dummy pixel unit and a dummy data line are located in the peripheral area;
wherein the dummy pixel unit comprises a dummy thin film transistor comprising a first electrode and a second electrode, wherein the first electrode is one of a source electrode and a drain electrode and is electrically connected to the dummy data line;
wherein the second electrode is the other of the source electrode and the drain electrode and comprises a first portion and a second portion separated by a first opening, and the first portion is located between the second portion and the first electrode; and
wherein the dummy pixel unit further comprises a pixel electrode electrically connected to the second portion of the second electrode, and the first portion of the second electrode is electrically isolated from the pixel electrode,
wherein a pixel unit and a data line are located in the display area, and the pixel unit comprises a thin film transistor comprising a third electrode and a fourth electrode, and wherein the third electrode is one of a source electrode and a drain electrode and is electrically connected to the data line, the fourth electrode is the other of the source electrode and the drain electrode and has no opening, and the pixel unit is configured to display an image, and
wherein a pattern of an orthographic projection of end portions of the first electrode, the first portion, and the second portion on the base substrate is identical to a pattern of an orthographic projection of end portions of the third electrode and the fourth electrode on the base substrate; and wherein, when superimposed upon each other, a pattern of an orthographic projection of the first opening on the base substrate overlaps with a pattern of an orthographic projection of a middle portion of the fourth electrode on the base substrate.

2. The display substrate according to claim 1 , wherein:
the dummy thin film transistor further comprises an active layer and a gate electrode,
in a same dummy thin film transistor, an orthographic projection of the gate electrode on the base substrate at least partially overlaps an orthographic projection of the active layer on the base substrate, and
the orthographic projection of the gate electrode on the base substrate at least partially overlaps an orthographic projection of the first portion of the second electrode on the base substrate.

3. The display substrate according to claim 2 , wherein:
in the same dummy thin film transistor, the orthographic projection of the active layer on the base substrate at least partially overlaps the orthographic projection of the first portion of the second electrode on the base substrate and does not overlap an orthographic projection of the second portion of the second electrode on the base substrate, and
an orthographic projection of the first opening on the base substrate does not overlap the orthographic projection of the active layer on the base substrate and does not overlap the orthographic projection of the gate electrode on the base substrate.

4. The display substrate according to claim 2 , wherein:
in the same dummy thin film transistor, the orthographic projection of the active layer on the base substrate at least partially overlaps the orthographic projection of the first portion of the second electrode on the base substrate and at least partially overlaps an orthographic projection of the second portion of the second electrode on the base substrate, and
an orthographic projection of the first opening on the base substrate falls into the orthographic projection of the active layer on the base substrate and the orthographic projection of the gate electrode on the base substrate.

5. The display substrate according to claim 2 , wherein in the same dummy thin film transistor, an orthographic projection of an edge of the first portion of the second electrode close to the first opening on the base substrate is aligned with an edge of the orthographic projection of the gate electrode on the base substrate.

6. The display substrate according to claim 2 , wherein in the same dummy thin film transistor, the orthographic projection of the gate electrode on the base substrate completely covers the orthographic projection of the first portion of the second electrode on the base substrate.

7. The display substrate according to claim 2 , wherein in the same dummy thin film transistor, the orthographic projection of the gate electrode on the base substrate partially overlaps an orthographic projection of the second portion of the second electrode on the base substrate.

8. The display substrate according to claim 2 , wherein:
the second electrode further comprises a third portion separated from the second portion by a second opening,
an orthographic projection of each of the first opening and the second opening on the base substrate does not overlap the orthographic projection of the gate electrode on the base substrate and does not overlap the orthographic projection of the active layer on the base substrate,
an orthographic projection of at least one of the first portion of the second electrode and the third portion of the second electrode on the base substrate at least partially overlaps the orthographic projection of the gate electrode on the base substrate and at least partially overlaps the orthographic projection of the active layer on the base substrate, and
the second portion of the second electrode is electrically connected to the pixel electrode through a first via hole structure.

9. The display substrate according to claim 1 , further comprising a common electrode,
wherein an electrode extension layer electrically connected to the common electrode and the dummy data line is further located in the peripheral area, and the electrode extension layer is made of a same material and arranged in a same layer as the first electrode, the second electrode and the dummy data line.

10. The display substrate according to claim 9 , wherein both ends of the dummy data line are electrically connected to the electrode extension layer to form a conductive loop that passes through the dummy data line and the electrode extension layer.

11. The display substrate according to claim 2 , further comprising a common electrode and a connection layer,
wherein an electrode extension layer connected to the common electrode is further located in the peripheral area, the connection layer is made of a same material and arranged in a same layer as the pixel electrode, and the connection layer is electrically connected to the common electrode through a second via hole structure and is electrically connected to the electrode extension layer through a third via hole structure.

12. The display substrate according to claim 11 , wherein:
the common electrode comprises a first common electrode extension portion and a second common electrode extension portion connected to each other, and an extension direction of the first common electrode extension portion crosses an extension direction of the second common electrode extension portion, and
wherein an orthographic projection of the connection layer on the base substrate at least partially overlaps an orthographic projection of the second common electrode extension portion on the base substrate, and an orthographic projection of the first common electrode extension portion on the base substrate at least partially overlaps an orthographic projection of the pixel electrode on the base substrate.

13. The displa

Assignees

• Chongqing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wang Wu
• Jiang Meicun
• Wang Xiaoyuan
• Bi Ruilin
• Feng Wenlong

Classifications

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/1368 Primary

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/133388 Primary

  with constructional differences between the display region and the peripheral region · CPC title

• G02F1/134309

  characterised by their geometrical arrangement · CPC title

• G02F1/136245

  having complementary transistors · CPC title