Liquid crystal display capable of preventing display defect and rubbing failure

Patent metadata

Field	Value
Publication number	US-10670930-B2
Application number	US-201715822180-A
Country	US
Kind code	B2
Filing date	Nov 26, 2017
Priority date	Nov 29, 2016
Publication date	Jun 2, 2020
Grant date	Jun 2, 2020

Abstract

A liquid crystal display preventing a light leakage is disclosed. The liquid crystal display includes gate lines and data lines disposed to cross over each other, a common line crossing over the data lines and disposed in parallel with the gate lines, a dummy data line crossing over the gate lines and disposed in parallel with the data lines, a dummy pixel electrode disposed in a dummy area formed by an outermost data line of the data lines, the dummy data line and first and second gate lines adjacent to each other among the gate lines; a pixel electrode disposed in a pixel area between first and second data lines adjacent to each other among the data lines and the first and second gate lines; and a common electrode disposed to overlap the pixel electrode and the dummy pixel electrode. The dummy pixel electrode is connected to the common line.

First claim

What is claimed is:

1. A liquid crystal display comprising:
gate lines and data lines crossing over each other;
a common line crossing over the data lines and disposed in parallel with the gate lines;
a dummy data line crossing over the gate lines and disposed in parallel with the data lines;
a dummy pixel electrode disposed in a dummy area formed by an outermost data line of the data lines, the dummy data line and first and second gate lines adjacent to each other among the gate lines;
a pixel electrode disposed in a pixel area between first and second data lines adjacent to each other among the data lines and the first and second gate lines; and
a common electrode overlapping the pixel electrode and the dummy pixel electrode,
wherein the dummy pixel electrode is electrically connected to the common line.

2. The liquid crystal display of claim 1 , wherein the dummy pixel electrode is connected to a protrusion extended from the common line, and the protrusion is disposed between the first gate line and the common line adjacent to each other.

3. The liquid crystal display of claim 1 , wherein the common line is connected to the common electrode in the dummy area and the pixel area.

4. The liquid crystal display of claim 1 , further comprising:
a dummy thin film transistor disposed in the dummy area, including a dummy gate electrode extended from the first gate line, a dummy source electrode overlapping the dummy gate electrode and extended from the dummy data line, and a dummy drain electrode overlapping the dummy gate electrode and spaced apart from the dummy source electrode by a predetermined distance; and
a thin film transistor disposed in the pixel area, including a gate electrode extended from the first gate line, a source electrode overlapping the gate electrode and extended from the first data line, and a drain electrode overlapping the gate electrode, spaced apart from the source electrode by a predetermined distance, and connected to the pixel electrode.

5. The liquid crystal display of claim 4 , wherein the dummy pixel electrode is connected to the common line between the dummy gate electrode and the gate electrode.

6. The liquid crystal display of claim 4 , wherein the gate lines and the common line are disposed on a substrate,
wherein the data line, the dummy source electrode, the dummy drain electrode, the source electrode, and the drain electrode are disposed on a gate insulating layer covering the gate lines and the common line.

7. The liquid crystal display of claim 6 , further comprising a first passivation layer covering the data line and the common electrode is disposed on the first passivation layer.

8. The liquid crystal display of claim 7 , further comprising a second passivation layer covering the common electrode and the dummy pixel electrode and the pixel electrode are disposed on the second passivation layer.

9. The liquid crystal display of claim 8 , wherein the dummy pixel electrode is connected to the common line exposed through a dummy pixel contact hole penetrating the second passivation layer, a first passivation layer, and the gate insulating layer.

10. The liquid crystal display of claim 1 , further comprising:
a gate link line disposed between the first gate line and a gate driving circuit supplying a gate driving signal to the gate lines; and
a connection pattern connecting the gate link line to the first gate line.

11. The liquid crystal display of claim 1 , further comprising a gate link line on the gate insulation and extended from a gate driving circuit supplying a gate driving signal, and connected to the gate line.

12. The liquid crystal display of claim 11 , further comprising a connection pattern connecting the gate link line to the gate line.

13. A liquid crystal display comprising:
a gate line and a common line disposed on a substrate and parallel with each other;
a gate insulation layer on the substrate and covering the gate line and the common line;
a data line on the gate insulation layer and crossing over the gate line;
a dummy data line on the gate insulation layer, crossing over the gate line, and disposed in parallel with the data line;
a first passivation layer on the gate insulation layer and covering the data line and a dummy data line;
a common electrode on the first passivation layer;
a second passivation layer on the first passivation layer and covering the common electrode;
a dummy pixel electrode in a dummy area of the second passivation layer; and
a pixel electrode disposed in a pixel area of the second passivation layer, and disposed in parallel with the dummy pixel electrode,
wherein the common electrode overlaps the pixel electrode and the dummy pixel electrode,
wherein the dummy pixel electrode is electrically connected to the common line through a dummy pixel contact hole.

14. The liquid crystal display of claim 13 , wherein the pixel electrode is connected to a drain electrode through a drain contact hole in the first and the second passivation layer.

15. The liquid crystal display of claim 13 , wherein the dummy pixel contact hole passes through the second passivation layer, the first passivation layer and the gate insulation layer.

16. The liquid crystal display of claim 13 , wherein the dummy pixel electrode is connected to a protrusion extended from the common line and the protrusion is disposed between the gate line and the common line adjacent to each other.

17. The liquid crystal display of claim 13 , wherein the common line is connected to the common electrode in the dummy area and the pixel area.

18. The liquid crystal display of claim 13 , further comprising:
a dummy thin film transistor disposed in the dummy area, including a dummy gate electrode extended from the gate line, a dummy source electrode extended from the dummy data line, and a dummy drain electrode spaced apart from the dummy source electrode by a predetermined distance; and
a thin film transistor disposed in the pixel area, including a gate electrode extended from the gate line, a source electrode extended from the data line, and a drain electrode spaced apart from the source electrode by a predetermined distance, and connected to the pixel electrode.

Assignees

• Lg Display Co Ltd

Inventors

• Jeong Seonghun
• Choi Hyuck
• KIM Haye
• Chun Minkyu
• Kim Kangil

Classifications

• G02F2201/40

  Arrangements for improving the aperture ratio · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/136 Primary

  Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit (G02F1/135 takes precedence) · CPC title

• G02F2201/123

  pixel · CPC title

• H01L27/124

  Electricity · mapped topic