Printed wiring board and method for manufacturing printed wiring board

Patent metadata

Field	Value
Publication number	US-11832397-B2
Application number	US-202017105768-A
Country	US
Kind code	B2
Filing date	Nov 27, 2020
Priority date	Dec 9, 2019
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

A printed wiring board includes a resin insulating layer, via conductors formed in the resin insulating layer, metal posts formed on the via conductors, respectively, and a solder resist layer formed on the resin insulating layer such that the metal posts have lower portions embedded in the solder resist layer and upper portions exposed from the solder resist layer, respectively. The metal posts are formed such that each of the metal posts has a top portion having a diameter in a range of 0.8 to 0.9 times a diameter of a respective one of the lower portions of the metal posts.

First claim

What is claimed is:

1. A printed wiring board, comprising:
a resin insulating layer;
a plurality of via conductors formed in the resin insulating layer;
a conductor layer formed on a surface of the resin insulating layer such that the plurality of via conductors and the conductor layer comprise an electroless plating film and an electrolytic plating film formed on the electroless plating film;
a plurality of metal posts formed on the electrolytic plating film of the conductor layer such that the plurality of metal posts is positioned on the plurality of via conductors, respectively; and
a solder resist layer formed on the resin insulating layer such that the conductor layer formed on the surface of the resin insulating layer is embedded in the solder resist layer and that the plurality of metal posts has a plurality of lower portions embedded in the solder resist layer and a plurality of upper portions protruding and exposed from the solder resist layer,
wherein the plurality of metal posts is formed such that each of the metal posts has a top portion having a diameter in a range of 0.8 to 0.9 times a diameter of a respective one of the lower portions of the metal posts and that each of the upper portions of the metal posts has a height measured from a surface of the solder resist layer in a range of 3 μm to 10 μm and is formed integrally with a respective one of the lower portions.

2. The printed wiring board according to claim 1 , further comprising:
a surface treatment layer formed on an exposed portion of each of the metal posts exposed from the solder resist layer.

3. The printed wiring board according to claim 2 , wherein the surface treatment layer includes a Ni/Pd/Au layer.

4. The printed wiring board according to claim 2 , wherein the surface treatment layer is formed on each of the metal posts such that a height of a surface of the surface treatment layer on a respective one of the metal posts is in a range of 4 μm to 11 μm relative to the solder resist layer.

5. The printed wiring board according to claim 1 , wherein the plurality of metal posts is formed such that each of the lower potions of the metal posts has a diameter in a range of 40 μm to 50 μm.

6. The printed wiring board according to claim 3 , wherein the surface treatment layer is formed on each of the metal posts such that a height of a surface of the surface treatment layer on a respective one of the metal posts is in a range of 4 μm to 11 μm relative to the solder resist layer.

7. The printed wiring board according to claim 2 , wherein the plurality of metal posts is formed such that each of the lower potions of the metal posts has a diameter in a range of 40 μm to 50 μm.

8. The printed wiring board according to claim 3 , wherein the plurality of metal posts is formed such that each of the lower potions of the metal posts has a diameter in a range of 40 μm to 50 μm.

9. The printed wiring board according to claim 4 , wherein the plurality of metal posts is formed such that each of the lower potions of the metal posts has a diameter in a range of 40 μm to 50 μm.

10. The printed wiring board according to claim 6 , wherein the plurality of metal posts is formed such that each of the lower potions of the metal posts has a diameter in a range of 40 μm to 50 μm.

11. The printed wiring board according to claim 2 , wherein the surface treatment layer is a Ni/Pd/Au layer.

12. The printed wiring board according to claim 11 , wherein the surface treatment layer is formed on each of the metal posts such that a height of a surface of the surface treatment layer on a respective one of the metal posts is in a range of 4 μm to 11 μm relative to the solder resist layer.

13. The printed wiring board according to claim 11 , wherein the plurality of metal posts is formed such that each of the lower potions of the metal posts has a diameter in a range of 40 μm to 50 μm.

14. The printed wiring board according to claim 12 , wherein the plurality of metal posts is formed such that each of the lower potions of the metal posts has a diameter in a range of 40 μm to 50 μm.

15. The printed wiring board according to claim 1 , wherein the plurality of metal posts is formed such that the plurality of metal posts comprises plating material.

16. A method for manufacturing a printed wiring board, comprising:
forming an electrolytic plating film on an electroless plating film exposed from a first plating resist layer such that a plurality of via conductors is formed in a plurality of openings in an outermost resin insulating layer and that a conductor layer including a conductor circuit is formed on a surface of the outermost resin insulating layer;
removing the first plating resist layer from the outermost resin insulating layer such that part of the electroless plating film covered by the first plating resist layer is exposed from the electrolytic plating;
forming a second plating resist layer on the outermost resin insulating layer such that the second plating resist layer has a plurality of openings on the plurality of via conductors, respectively;
applying plating in the plurality of openings in the second plating resist layer such that a plurality of metal posts is formed on the electrolytic plating film of the conductor layer and that the plurality of metal posts is positioned on the plurality of via conductors, respectively;
removing the second plating resist layer from the outermost resin insulating layer such that the conductor circuit formed on the outermost resin insulating layer and the part of the electroless plating film exposed from the electrolytic plating are exposed;
applying first etching on the part of the electroless plating film exposed from the electrolytic plating film such that the part of the electroless plating film exposed from the electrolytic plating film is removed from the outermost resin insulating layer;
forming a solder resist layer on the outermost resin insulating layer such that the conductor layer including the conductor circuit and the plurality of metal posts formed on the outermost resin insulating layer are embedded in the solder resist layer;
reducing a film thickness of the solder resist layer such that the conductor layer including the conductor circuit is embedded in the solder resist layer and that the plurality of metal posts has a plurality of upper portions protruding and exposed from the solder resist layer and a plurality of lower portions embedded in the solder resist layer, respectively; and
applying second etching on the upper portions of the plurality of metal posts such that each of the metal posts has a top portion having a diameter in a range of 0.8 to 0.9 times a diameter of a respective one of the lower portions of the metal posts and that each of the upper portions of the metal posts has a height measured from the surface of the solder resist layer in a range of 3 μm to 10 μm and is formed integrally with a respective one of the lower portions.

17. The method for manufacturing a printed wiring board according to claim 16 , further comprising:
forming a surface treatment layer on an exposed portion of each of the metal posts exposed from the solder resist layer.

18. The method for manufacturing a printed wiring board according to claim 16 , further comprising:
forming the plurality of via openings in the outermost resin insulating layer;
forming the electroless plating film on the surface of the outermost resin insulating layer and in the plurality of via openings; and
forming a first plating resist layer on the electroless plating film such t

Assignees

• Ibiden Co Ltd

Inventors

• Awazu Masashi
• Kojima Keisuke

Classifications

• H05K3/3452 Primary

  Solder masks · CPC title

• H05K1/116

  Lands, clearance holes or other lay-out details concerning the surrounding of a via · CPC title

• H05K3/422

  characterised by electroless plating method; pretreatment therefor · CPC title

• H05K3/4661

  Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor (other insulating materials H05K3/387) · CPC title

• H05K3/4679

  Aligning added circuit layers or via connections relative to previous circuit layers · CPC title