Integrated circuits and methods for forming integrated circuits

Patent metadata

Field	Value
Publication number	US-11830788-B2
Application number	US-202117303270-A
Country	US
Kind code	B2
Filing date	May 25, 2021
Priority date	Dec 17, 2018
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.

First claim

What is claimed is:

1. A method for forming an integrated circuit, the method comprising:
forming a first portion of a wiring layer stack of the integrated circuit on a semiconductor substrate of the integrated circuit;
forming a transistor on the first portion of the wiring layer stack,
wherein forming the transistor comprises forming an embedded layer of the transistor,
wherein the embedded layer has a thickness of less than 10 nm,
wherein the embedded layer comprises at least one two-dimensional crystalline layer comprising more than 10% metal atoms; and

forming a second portion of the wiring layer stack on the transistor so that the transistor is embedded in the wiring layer stack.

2. The method according to claim 1 ,
wherein the embedded layer is a thin film crystal layer.

3. The method according to claim 2 , further comprising
converting a crystal phase of at least a portion of the thin film crystal layer from a first crystal phase into a second crystal phase.

4. The method according to claim 3 ,
wherein the crystal phase is converted by at least one of chemical treatment, laser treatment or electron beam treatment of the portion of the thin film crystal layer.

5. The method according to claim 2 ,
wherein forming the thin film crystal layer comprises:
forming a layer comprising at least a first and a second portion of different metals; and
heating the layer in a gas atmosphere to transform the metal of the first portion into a thin film crystal material having a first crystal phase and the metal of the second portion into a thin film crystal material having a second crystal phase.

6. The method according to claim 2 ,
wherein forming the thin film crystal layer comprises:
forming first metal portions of a metal in a layer and transforming the metal of the first metal portions into thin film crystal material having a first crystal phase; and
forming second metal portions of the metal in the layer next to the first metal portions and transforming the metal of the second metal portions into thin film crystal material having a second crystal phase, so that the formed thin film crystal layer has portions comprising the crystal material having the first crystal phase adjacent to portions comprising the crystal material having the second crystal phase.

Assignees

• Intel Corp

Inventors

• Naylor Carl
• Agrawal Ashish
• Alaan Urusa
• Jezewski Christopher
• Kobrinsky Mauro
• Lin Kevin
• Sharma Abhishek Anil

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W40/613 Primary

  for stacked arrangements of a plurality of semiconductor devices · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D88/01

  Manufacture or treatment · CPC title