Selective passivation and selective deposition

Patent metadata

Field	Value
Publication number	US-11830732-B2
Application number	US-202117470177-A
Country	US
Kind code	B2
Filing date	Sep 9, 2021
Priority date	Oct 2, 2018
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.

First claim

What is claimed is:

1. A method of selective deposition on a second dielectric surface of a substrate relative to a first metal or metallic surface of the substrate, the method comprising, in order:
treating the first and second surfaces by exposing the substrate to a silane;
selectively forming a polymer layer from vapor phase reactants on the first surface relative to the second surface;
baking the polymer layer;
etching the polymer layer for a first polymer etch time to form a polymer layer leading edge, wherein at least some of the polymer layer remains on the first surface after etching; and
depositing a dielectric layer on the second surface of the substrate from vapor phase reactants,
wherein the first polymer etch time is selected to control a position of an edge of the dielectric layer to be deposited relative to a boundary between the underlying first and second surfaces.

2. The method of claim 1 , wherein etching comprises an isotropic etch.

3. The method of claim 1 , wherein etching comprises an anisotropic etch.

4. The method of claim 1 , wherein a polymer is formed on the second surface.

5. The method of claim 4 , wherein the first polymer etch time is selected to remove a portion of the polymer from the second surface but leave the polymer layer leading edge that extends over the boundary between the underlying first and second surfaces.

6. The method of claim 5 , wherein depositing the dielectric layer is followed by removal of the polymer layer, resulting in a gap between an edge of the deposited dielectric layer and the boundary between the underlying first and second surfaces.

7. The method of claim 4 , wherein the first polymer etch time is selected to completely remove any polymer from the second surface and leave the polymer layer leading edge aligned with the boundary between the underlying first and second surfaces.

8. The method of claim 7 , wherein after depositing the dielectric layer an edge of the deposited dielectric layer is aligned with the boundary between the underlying first and second surfaces.

9. The method of claim 4 , wherein the first polymer etch time is selected to completely remove any polymer from the second surface and to remove a portion of the polymer layer from the first surface.

10. The method of claim 9 , wherein the deposited dielectric layer extends over the boundary between the underlying first and second surfaces.

11. The method of claim 1 , wherein the silane comprises an alkylaminosilane.

12. The method of claim 11 , wherein treating comprises exposing the substrate to N-(trimethylsilyl)dimethylamine (TMSDMA) or trimethylchlorosilane.

13. The method of claim 1 , wherein baking comprises heating the substrate to a temperature of about 200 to about 500° C.

14. The method of claim 1 , wherein selectively forming the polymer layer comprises selectively vapor depositing an organic polymer layer on the first surface.

15. The method of claim 14 , wherein the organic polymer layer is a polyimide layer.

16. The method of claim 1 , wherein the dielectric layer is deposited by an atomic layer deposition process.

17. The method of claim 1 , wherein the dielectric layer comprises a metal oxide.

18. The method of claim 17 , wherein the metal oxide comprises a dielectric transition metal oxide.

19. The method of claim 1 , wherein the dielectric layer comprises ZrO 2 .

20. The method of claim 1 , wherein the substrate comprises a partially fabricated integrated circuit with an embedded feature in which the first metal or metallic surface is flush with the second dielectric surface.

Assignees

• Asm Ip Holding Bv

Inventors

• Maes Jan Willem Hub
• Givens Michael Eugene
• Haukka Suvi P
• Paruchuri Vamsi
• Raaijmakers Ivo Johannes
• Deng Shaoren
• Illiberi Andrea
• Tois Eva E
• Longrie Delphine
• Pore Viljami

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P72/0471

  comprising at least one ion or electron beam chamber · CPC title

• H10P70/27

  during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers · CPC title

• H10P14/69391 Primary

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/6514

  by exposure to a plasma · CPC title