Ceramic electronic device

Patent metadata

Field	Value
Publication number	US-11830674-B2
Application number	US-202217728130-A
Country	US
Kind code	B2
Filing date	Apr 25, 2022
Priority date	May 31, 2021
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

A ceramic electronic device includes a multilayer chip in which a plurality of dielectric layers and a plurality of internal electrode layers are stacked. The plurality of internal electrode layers include Au. Each of the plurality of internal electrode layers includes an Au-containing layer of which an Au concentration with respect to all detected elements is 5 at % or more, on an interface between the each of the plurality of internal electrode layers and a dielectric layer next to the each of the plurality of internal electrode layers. A relationship of C≤500×t/T is satisfied when a thickness of the each of the plurality of internal electrode layers is T nm, a thickness of the Au-containing layer is t nm, and an Au concentration with respect to a total of Ni and Au in a whole of the each of the plurality of internal electrode layers is C at %.

First claim

What is claimed is:

1. A ceramic electronic device comprising:
a multilayer chip in which a plurality of dielectric layers of which a main component is ceramic and a plurality of internal electrode layers are stacked,
wherein a main component of the plurality of internal electrode layers is Ni,
wherein the plurality of internal electrode layers include Au,
wherein each of the plurality of internal electrode layers includes an Au-containing layer of which an Au concentration with respect to all detected elements is 5 at % or more, on an interface between the each of the plurality of internal electrode layers and a dielectric layer next to the each of the plurality of internal electrode layers, and
wherein a relationship of C≤500×t/T is satisfied when a thickness of the each of the plurality of internal electrode layers is T nm, a thickness of the Au-containing layer is t nm, and an Au concentration with respect to a total of Ni and Au in a whole of the each of the plurality of internal electrode layers is C at %.

2. The ceramic electronic device as claimed in claim 1 , wherein the thickness t nm is 1 nm or less than 1 nm.

3. The ceramic electronic device as claimed in claim 1 , wherein the Au concentration with respect to all detected elements in a whole of the Au-containing layer is 5 at % or more and 15 at % or less.

4. The ceramic electronic device as claimed in claim 1 , wherein a Ni concentration is higher than the Au concentration in a surface portion of each of the dielectric layers on the side of the each of the internal electrode layers.

5. The ceramic electronic device as claimed in claim 1 , wherein the Au concentration with respect to a total of Ni and Au in a whole of the each of the internal electrode layers is 20 at % or less.

6. The ceramic electronic device as claimed in claim 1 , wherein the Au concentration with respect to a total of Ni and Au in a portion of the internal electrode layers other than the Au-containing layer is 0.01 at % or more and 20 at % or less.

7. The ceramic electronic device as claimed in claim 1 , wherein the plurality of dielectric layers include barium titanate.

8. The ceramic electronic device as claimed in claim 1 , wherein the thickness T of the each of the plurality of internal electrode layers is 10 nm or more and 1000 nm or less.

9. A ceramic electronic device comprising:
a multilayer chip in which a plurality of dielectric layers of which a main component is ceramic and a plurality of internal electrode layers are stacked,
wherein a main component of the plurality of internal electrode layers is Ni,
wherein the plurality of internal electrode layers includes Au,
wherein each of the plurality of internal electrode layers include an Au-containing layer of which an Au concentration with respect to all detected elements is 5 at % or more, on an interface between each of the plurality of dielectric layers and each of the plurality of internal electrode layers, and
wherein a difference between an Au concentration with respect to all detected elements of a whole of the Au containing layer and an Au concentration with respect to all detected elements of a whole of a portion other than the Au-containing layer in each of the plurality of internal electrode layers is 0.5 at % or more.

10. The ceramic electronic device as claimed in claim 9 , wherein the difference between the Au concentration with respect to all detected elements of the whole of the Au containing layer and the Au concentration with respect to all detected elements of the whole of the portion other than the Au-containing layer in each of the plurality of internal electrode layers is 15 at % or less.

11. The ceramic electronic device as claimed in claim 9 , wherein the Au concentration with respect to all detected elements in the whole of the portion other than the Au-containing layer in each of the plurality of internal electrode layers is 0 at % or more and 4.5 at % or less.

Assignees

• Taiyo Yuden Kk

Inventors

• Masuda Hidetoshi
• Ryu Minoru
• Atsumi Teruo

Classifications

• H01G4/008 Primary

  Selection of materials · CPC title

• H01G4/1227

  based on alkaline earth titanates · CPC title

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/12

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title