Laminated ceramic capacitor and method for manufacturing laminated ceramic capacitor
US-2015155098-A1 · Jun 4, 2015 · US
Ceramic electronic device and manufacturing method of the same
US2022139630A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2022139630-A1 |
| Application number | US-202117372401-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jul 9, 2021 |
| Priority date | Oct 30, 2020 |
| Publication date | May 5, 2022 |
| Grant date | — |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A ceramic electronic device includes a multilayer chip in which a plurality of dielectric layers of which a main component is ceramic and a plurality of internal electrode layers are stacked. The plurality of internal electrode layers include Ni, Sn and Au.
First claim
Opening claim text (preview).
What is claimed is: 1 . A ceramic electronic device comprising: a multilayer chip in which a plurality of dielectric layers of which a main component is ceramic and a plurality of internal electrode layers are stacked, wherein the plurality of internal electrode layers include Ni, Sn and Au. 2 . The ceramic electronic device as claimed in claim 1 , wherein a total amount of Sn and Su with respect to Ni in the plurality of internal electrode layers is 0.01 at % or more and 95 at % or less. 3 . The ceramic electronic device as claimed in claim 2 , wherein the total amount of Sn and Au with respect to Ni in the plurality of internal electrode layers is 0.2 at % or more and 10 at % or less. 4 . The ceramic electronic device as claimed in claim 1 , wherein an amount of Au is smaller than an amount of Sn in the plurality of internal electrode layers. 5 . The ceramic electronic device as claimed in claim 1 , wherein a Sn concentration near each interface between the plurality of internal electrode layers and the plurality of dielectric layers is larger than the Sn concentration in each center portion in a thickness direction in the plurality of internal electrode layers. 6 . The ceramic electronic device as claimed in claim 1 , wherein an Au concentration near each interface between the plurality of internal electrode layers and the plurality of dielectric layers is larger than the Au concentration in each center portion in a thickness direction in the plurality of internal electrode layers. 7 . A manufacturing method of a ceramic electronic device comprising: forming each of stack units by forming each of internal electrode patterns on each of dielectric green sheets, the each of internal electrode patterns including Ni, Sn and Au; forming a multilayer structure by stacking the each of stack units; and firing the multilayer structure. 8 . The manufacturing method as claimed in claim 7 , wherein, in the forming of the each of stack units, the each of internal electrode patterns is formed on the each of dielectric green sheet by a vacuum deposition process.
Assignees
Inventors
Classifications
characterised by the material of the terminals · CPC title
Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title
- H01G4/30Primary
Stacked capacitors (H01G4/33 takes precedence) · CPC title
- H01G4/008Primary
Selection of materials · CPC title
electrically connecting two or more layers of a stacked or rolled capacitor · CPC title
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Frequently asked questions
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- What does patent US2022139630A1 cover?
- A ceramic electronic device includes a multilayer chip in which a plurality of dielectric layers of which a main component is ceramic and a plurality of internal electrode layers are stacked. The plurality of internal electrode layers include Ni, Sn and Au.
- Who is the assignee on this patent?
- Taiyo Yuden Kk
- What technology area does this patent fall under?
- Primary CPC classification H01G4/30. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu May 05 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).